EN

STANDBY

SOIC

P-GATE

SS

N-GATE

COMP

GND

FB

SYNC

Top View

11

12

13

14

2

3

4

1

8

9

10

5

6

7

Si9150

Vishay Siliconix

www.vishay.com

4

Document Number: 70020

S-40752—Rev. F, 19-Apr-04

PIN CONFIGURATION AND ORDERING INFORMATION

ORDERING INFORMATION

Part Number

Temperature Range

Package

Si9150CY

Si9150CY-T1

0 to 70_C

Si9150CY-T1—E3

SOIC-14

Si9150DY

SOIC-14

Si9150DY-T1

−40 to 85_C

Si9150DY-T1—E3

40 to 85 C

PIN DESCRIPTION

Pin 1: EN

When this pin is low, the IC is shut down. After a low signal is

ground; N-GATE, STBY and Soft-Start are grounded; and

P-GATE is pulled high. The current consumption is no more

than 100 mA in this state. This input’s threshold has substantial

hysteresis so that a capacitor to GND can be used to delay

exceeded, one clock cycle elapses before N-GATE and

resistor and is pulled down internally when the current limit is

triggered.

Pin 2: STBY

Has a function similar to EN. The differences are that the EN

pin is unaffected, that the reference is still available, that bias

currents are still present internally, and that this pin’s pull up

current is present. This pin should be used to disable an

application if the reference voltage is still needed.

Pin 3: Soft-Start (SS)

This pin limits the maximum voltage that the error amplifier can

output. A capacitor between this pin and ground will limit the

rate at which the duty factor can increase during initial power

up, during a restart when EN or STBY goes high, or after the

current limit is triggered. A capacitor here can prevent an

application from triggering the Si9150’s current limit during

startup. Soft-Start is pulled low if either EN or STBY is low.

Pin 4: Compensation (COMP)

This pin is tied directly to the output of the error amplifier. The

feedback network which insures the stability of an application

uses this pin. COMP settles low when either EN or STBY is

pulled low.

Pin 5: Feedback (FB)

This pin is attached directly to the inverting input of the error

amplifier. This pin is used to regulate the power supply’s output

voltage.

The internal 2.5-V reference generator is attached to this pin

through a 5-W resistor. A 0.1-mF bypass capacitor is needed to

suppress noise. Also note that the generator has an open

emitter; it will not pull down. The maximum current that the

generator will source before it current limits is about 10 mA.

Many parts of the IC use this voltage, so it is important not to

overload the reference generator.

This pin should be attached to the switched node (the drains

of the application’s p-channel and n-channel MOSFETs). If the

P-GATE is low, the current limit is activated. The current limit

is relatively slow to prevent false triggering due to noise.

Activating the current limit causes EN to be pulled to GND.

Figure 1.

Pin 8: SYNC

This pin forces the clock to reset when low, and is also pulled

low when the clock resets itself. Thus if several Si9150’s have

their sync pins shorted together, they will be synchronized; the

shortest duration clock will control the other clocks.