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ADRF6720-27-EVALZ Datasheet(PDF) 3 Page - Analog Devices

No. de pieza ADRF6720-27-EVALZ
Descripción Electrónicos  Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs
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ADRF6720-27-EVALZ Datasheet(HTML) 3 Page - Analog Devices

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ADRF6720-27
Data Sheet
Rev. B | Page 2 of 43
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 18
LO Generation Block ................................................................. 18
Baseband...................................................................................... 21
Active Mixers .............................................................................. 21
Serial Port Interface.................................................................... 22
Basic Connections for Operation................................................. 23
Power Supply and Grounding................................................... 23
Baseband Inputs.......................................................................... 24
LO Input ...................................................................................... 24
Loop Filter................................................................................... 24
RF Output.................................................................................... 24
Applications Information .............................................................. 25
DAC to I/Q Modulator Interfacing.......................................... 25
Baseband Bandwidth ................................................................. 26
Carrier Feedthrough Nulling.................................................... 26
Sideband Suppression Optimization ....................................... 26
Linearity....................................................................................... 27
LO Amplitude and Common-Mode Voltage.......................... 27
Operating Out of Frequency Range......................................... 28
Spurious Performance ............................................................... 28
Layout .......................................................................................... 29
Characterization Setups................................................................. 30
Register Map ................................................................................... 32
Register Details ............................................................................... 33
Outline Dimensions....................................................................... 43
Ordering Guide .......................................................................... 43
REVISION HISTORY
9/15—Rev. A to Rev. B
Changed RFOUT = 4 dBm to RFOUT ≈ 4 dBm, and USB to
Sideband Suppression ................................................... Throughout
Changes to Spurious Performance Section and Figure 59........ 28
Changes to Figure 60...................................................................... 29
3/15—Rev. 0 to Rev. A
Added Spurious Performance Section and Figure 57 to
Figure 59; Renumbered Sequentially........................................... 28
Added Figure 60 ............................................................................. 29
10/14—Revision 0: Initial Version


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