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DM9102 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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DM9102 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 77 page DM9102A Single Chip Fast Ethernet NIC controller 10 Final Version: DM9102A-DS-F03 August 28, 2000 Direct mode Pin No. 128QFP/128TQFP Pin Name I/O Description 62 MD0/EEDI I Boot ROM data input/EEPROM data in This is multiplexed pin used by EEDI and MD0. When boot ROM is selected, it acts as boot ROM data input. When ROMCS select the EEPROM, the DM9102A will read the contents of EEPROM serially through this pin. 63,64,65,66,67,68,69 MD1~MD7 I Boot ROM data input bus MD1 is also a reset latch pin. It is Boot ROM address and data bus when normal operation. When at power on reset, it is used to pull up or down externally through a resister to select the WOL as pulse orlevel signal. 0 = WOL pulse mode (default) 1 = WOL level mode MD2 is also a reset latch pin. It is Boot ROM address and data bus when normal operation. When at power on reset, it is used to pull up or down externally through a resister to select the PME as pulse or level signal. 0 = PME pulse mode (default) 1 = PME level mode MD7 is also a reset latch pin. It is Boot ROM address and data bus when normal operation. When at power on reset, it is used to pull up or down externally through a resister to select LED mode. 0 = LED mode 0 (default) 1 = LED mode 1 72 ROMCS O Boot ROM or EEPROM chip selection. 73 MA0/WMODE O Boot ROM address output line/WOL mode selection This multiplexed pin acts as boot ROM address output bus during normal operation. When RST# is active, it is used to pull up or down externally through a resister to select WOL High active or LOW active.(WMODE) 0 = WOL high active (default) 1 = WOL low active 74 MA1/PCIMODE# O, LI Boot ROM address output signal/PCI mode selection This multiplexed pin acts as a boot ROM address output signal during normal operation. When RST# is active, it acts as the input system type. If the DM9102A is used in a CardBus system, this pin should be connected to a pull-up resistor; otherwise, the DM9102A consider the host as a PCI system. 0 = PCI mode (default) 1 = CardBus mode 77 MA2 O Boot ROM address output signal 78 MA3/EEDO O Boot ROM address output/EEPROM data out This is multiplexed pin used by MA3 and EEDO. |
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