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CAT25020LI-G Datasheet(PDF) 6 Page - ON Semiconductor |
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CAT25020LI-G Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 15 page CAT25010, CAT25020, CAT25040 www.onsemi.com 6 Table 10. STATUS REGISTER 7 6 5 4 3 2 1 0 1 1 1 1 BP1 BP0 WEL RDY Table 11. BLOCK PROTECTION BITS Status Register Bits Array Address Protected Protection BP1 BP0 0 0 None No Protection 0 1 CAT25010: 060−07F, CAT25020: 0C0−0FF, CAT25040: 180−1FF Quarter Array Protection 1 0 CAT25010: 040−07F, CAT25020: 080−0FF, CAT25040: 100−1FF Half Array Protection 1 1 CAT25010: 000−07F, CAT25020: 000−0FF, CAT25040: 000−1FF Full Array Protection WRITE OPERATIONS The CAT25010/20/40 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of the memory location(s) to be written must be outside the protected area, as defined by BP0 and BP1 bits from the status register. Write Enable and Write Disable The internal Write Enable Latch and the corresponding Status Register WEL bit are set by sending the WREN instruction to the CAT25010/20/40. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3. The WREN instruction must be sent prior to any WRITE or WRSR instruction. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write operations by resetting the WEL bit, will protect the device against inadvertent writes. Figure 3. WREN Timing SCK SI SO 00 0 0 0 11 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) CS Figure 4. WRDI Timing SCK SI SO 0 0 000 10 0 HIGH IMPEDANCE Dashed Line = mode (1, 1) CS |
Número de pieza similar - CAT25020LI-G |
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Descripción similar - CAT25020LI-G |
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