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LM2637 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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LM2637 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 17 page Applications Information (Continued) During normal operation, if V CC voltage drops below 3.6V, the internal circuitry will go into power-on-reset again. The hysteresis helps decrease the noise sensitivity on the V CC pin. After soft start ends and during normal operation, if the con- verter output voltage exceeds 118% of DAC output voltage, the LM2637 will lock into over-voltage protection mode. The high-side drive will be low, and the low-side drive will be high. There are two ways to clear the mode. One is to cycle V CC voltage once. The other is to toggle the EN level. After the over-voltage protection mode is cleared, the LM2637 will en- ter the soft start session and start over. Linear Section — The linear section does not go through a soft start. Whenever the soft start of the switching section begins, the linear section immediately applies the required gate voltages or base currents for external power transistors. There is an under-voltage latch-off for the linear section. If after soft start ends, SNS2 or SNS3 is below 0.63V, the cor- responding gate drive will be disabled and PWGD pin will be pulled low. Normal Operation Switching Section — In the normal operation mode, the LM2637 regulates the converter output voltage by adjusting the duty ratio. The output voltage is determined by the 5-bit VID code set by the user or MPU. The PWM frequency is set by an external resistor between FREQ pin and ground. The resistance needed for a desired PWM frequency can be determined by the following equa- tion: (1) For example, if the desired PWM frequency is 300 kHz, the resistance should be around 84 k Ω. The minimum allowable PWM frequency is 5 kHz. Linear Section — Under steady state operation, the linear section supplies the appropriate gate voltage or base current to correctly bias the external pass transistor so that the volt- age drop across the transistor is the right value. Resetting the LM2637 When the LM2637 detects an abnormal condition such as switching regulator over voltage, it will latch itself off partially or completely. To reset the LM2637, either EN or V CC voltage has to be toggled. Another more subtle way to recover is to float all the VID pins and reapply the correct code. Gate Drives Switching Section — The switching controller has two gate drives that are suitable for driving external power N-FETs in a synchronous buck topology. The voltage for the two FET drivers is supplied by the V DD pin. This VDD voltage should be at least one V GS(th) higher than converter input voltage to be able to fully enhance the high-side FET. In a typical PC motherboard application, it is recommended that 12V be ap- plied to V DD, and 5V be used as the input voltage for the switcher. A charge pump is not recommended since the lin- ear sections need a stable V DD voltage to minimize high fre- quency noise. ForaV DD of 12V, the peak gate charging current is typically 2A, and the peak gate discharging current is typically 6A, well suited for high speed switching. The LM2637 gate drives are of BiCMOS design. Unlike some bipolar control ICs, the gate drive has rail-to-rail swing that ensures no spurious turn-on due to capacitive coupling. Another feature of the FET gate drives is the adaptive non-overlapping mechanism. A gate drive is not turned on until the other is fully off. The dead time in between is typi- cally 20 ns. This avoids the potential shoot-through problem and helps improve efficiency. Linear Section — The gate drives of the linear section can put out a maximum continuous current of about 40 mA. The typical low gate voltage is 1.2V. Load Transient Response Switching Section — In a typical modern MPU application such as the M II, Pentium II and K6-2 core power supply, load transient response is a critical issue. The LM2637 uti- lizes the conventional voltage feedback technology as the primary feedback control method. When the load transient happens, the error in the output voltage level is fed to the er- ror amplifier. The output of the error amplifier is then com- pared with an internally generated PWM ramp signal and the result of the comparison is a series of pulses with certain duty ratios. These pulses are then used to control the on and off of the FET gate drives. In this way, the error in the output voltage gets corrected by the change in the duty ratio of the FET switches. During a large load transient, depending on the compensation design, the change in duty ratio usually begins within one switching cycle. Refer to the Design Con- siderations section for more details. Besides the voltage feedback control loop, the LM2637 also has a pair of fast comparators (the MIN and MAX compara- tors) to help maintain the output voltage during a large and fast load transient. The trip points of the comparators are set to ±5% of the DAC output voltage. When the load transient is so large that the output voltage goes outside the ±5% win- dow, the MIN or MAX comparator will bypass the primary voltage control loop and immediately set the duty ratio to ei- ther 100% or 0%. This provides the fastest possible way to react to such a large load transient in a conventional buck converter. Linear Section — The linear section has a high control band- width. Depending on external components selected, the typi- cal bandwidth can be as high as 1.2 MHz. The user may choose to lower this bandwidth and have a better noise im- munity by adding a small capacitor (1 nF to 10 nF) between the gate output and ground. Power Good Signal The power good signal is to indicate whether all three output voltages are within their corresponding range. The range for the switching regulator is set to a typical ±10% window of the DAC output voltage. The range for the linear regulator is 0.63V to infinity. During soft start, the power good signal is kept low. At the completion of soft start, all three output volt- ages are checked and the PWGD pin will be asserted if they are all within specified range. During normal operation, whenever a voltage goes out of the specified range for more than about 3 µs, PWGD pin will be pulled low. Over-Voltage Protection Switching Section — When the output voltage exceeds 118% of the DAC output voltage any time beyond the soft start, the switching section will enter over-voltage protection mode and shuts itself down. The upper gate drive will be held low while the lower gate drive will be held high. PWGD www.national.com 9 |
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