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9ZXL1231AKLFT Datasheet(PDF) 5 Page - Integrated Device Technology |
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9ZXL1231AKLFT Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 18 page REVISION J 05/25/16 5 12-OUTPUT DB1200ZL 9ZXL1231 DATASHEET Pin Descriptions (cont.) Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9ZXL1231. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PIN # PIN NAME TYPE DESCRIPTION 38 DIF_5 OUT HCSL true clock output 39 DIF_5# OUT HCSL Complementary clock output 40 VDD PWR Power supply, nominal 3.3V 41 GND GND Ground pin. 42 DIF_6 OUT HCSL true clock output 43 DIF_6# OUT HCSL Complementary clock output 44 vOE6# IN Active low input for enabling DIF pair 6. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 45 vOE7# IN Active low input for enabling DIF pair 7. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 46 DIF_7 OUT HCSL true clock output 47 DIF_7# OUT HCSL Complementary clock output 48 GND GND Ground pin. 49 VDDIO PWR Power supply for differential outputs 50 DIF_8 OUT HCSL true clock output 51 DIF_8# OUT HCSL Complementary clock output 52 vOE8# IN Active low input for enabling DIF pair 8. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 53 vOE9# IN Active low input for enabling DIF pair 9. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 54 DIF_9 OUT HCSL true clock output 55 DIF_9# OUT HCSL Complementary clock output 56 VDDIO PWR Power supply for differential outputs 57 VDD PWR Power supply, nominal 3.3V 58 GND GND Ground pin. 59 DIF_10 OUT HCSL true clock output 60 DIF_10# OUT HCSL Complementary clock output 61 vOE10# IN Active low input for enabling DIF pair 10. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 62 vOE11# IN Active low input for enabling DIF pair 11. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 63 DIF_11 OUT HCSL true clock output 64 DIF_11# OUT HCSL Complementary clock output 65 epad GND Connect epad to Ground PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Supply Voltage VDDx 4.6 V 1,2 Input Low Voltage VIL GND-0.5 V 1 Input High Voltage VIH Except for SMBus interface VDD+0.5 V 1,3 Input High Voltage VIHSMB SMBus clock and data pins 5.5 V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 4.6V. |
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