Datasheet

Datasheet

8/40

TSZ02201-0C1C0E900620-1-2

© 2016 ROHM Co., Ltd. All rights reserved.

21.Sep.2016 Rev.003

www.rohm.com

TSZ22111 • 15 • 001

BD28412MUV

Top

2 Internal Layers

Bottom

Copper Pattern

Thickness

Copper Pattern

Thickness

Copper Pattern

Thickness

Footprints and Traces

70µm

74.2mm x 74.2mm

35µm

74.2mm x 74.2mm

70µm

(Note 8) This thermal via connects with the copper pattern of all layers..

Use a thermal design that allows for a sufficient margin in consideration of power dissipation under actual operating

conditions. This IC exposes its frame at the backside of package. Note that this part is assumed to use after providing heat

dissipation treatment to improve heat dissipation efficiency. Try to occupy as wide as possible with heat dissipation pattern

not only on the board surface but also the backside.

Recommended Operating Conditions (Ta= -25°C to +85°C)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Supply Voltage

4.5

-

13

V

VCCA, VCCP1, VCCP2

Load Impedance

(Note 9)

5.4

-

-

Ω

BTL

3.2

-

-

Ω

PBTL

High Level Input Voltage

2.0

-

3.3

V

FSEL0, FSEL1, FSEL2,

MUTEX, PDX

Low Level Input Voltage

0

-

0.8

V

FSEL0, FSEL1, FSEL2,

MUTEX, PDX

Low Level Output Voltage

-

-

0.8

V

(Note 9) Tj<150°C