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SM813xxxUMG-TR Datasheet(PDF) 5 Page - Microchip Technology |
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SM813xxxUMG-TR Datasheet(HTML) 5 Page - Microchip Technology |
5 / 21 page 2016 Microchip Technology Inc. DS20005538B-page 5 SM813XXX Note 1: See Figure 4-6. 2: Output-to-output skew is defined as skew between outputs at the same supply voltage and with equal load conditions. It is measured at the output differential crossing points. 3: Output-to-output skew is only defined for outputs in the same PLL bank [A:B, C:D] with the same output logic type setting. 4: All phase noise measurements were taken with an Agilent 5052B phase noise system. 5: Measured using a 52.0833 MHz crystal as the input reference source. There are sufficient feedback dividers to support below 20 MHz, down to about 12 MHz, but phase noise performance will be impacted. Please contact Microchip TCG Applications for more information. Equivalent Series Resistance (ESR) — — 80 Ω Saunders 250B, 25Ω Pi Network Load Capacitance (CL) — 8 — pF Device Equivalent Load Shunt Capacitor, C0 — 1 2 pF — Correlation Drive Level — 10 100 µW — TABLE 1-7: AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C. Symbol Parameters Min. Typ. Max. Units Conditions FIN Input Frequency 31.25 50 156.25 MHz XO FOUT Output Frequency 12 — 850 MHz LVPECL, LVDS, HCSL 12 — 250 LVCMOS tr/tf Output Rise/Fall Time (Note 1) 85 135 350 ps LVPECL Output 85 140 300 LVDS Output 175 300 450 HCSL Output 100 200 400 LVCMOS Output ODC Output Duty Cycle 45 50 55 % All Output Frequencies 48 50 52 <350 MHz Output Frequencies TSKEW Output-to-Output Skew (Note 2, Note 3) —— 50 ps Note 3, Same Output Bank TLOCK PLL Lock Time — 5 20 ms VDD = 90% Tjit(Ø) RMS Phase Jitter (Note 4, Note 5) — 112 150 fs Integration Range 12 kHz - 20 MHz — 64 — Integration Range 1.875 MHz - 20 MHz TABLE 1-6: CRYSTAL CHARACTERISTICS (CONTINUED) Parameters Min. Typ. Max. Units Conditions |
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