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74LVC16373APVG8 Datasheet(PDF) 2 Page - Integrated Device Technology |
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74LVC16373APVG8 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 6 page INDUSTRIALTEMPERATURERANGE 2 IDT74LVC16373A 3.3VCMOS16-BIT TRANSPARENT D-TYPE LATCH SSOP/ TSSOP TOP VIEW PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, –50 mA IOK VI < 0 or VO < 0 ICC Continuous Current through each ±100 mA ISS VCC or GND ABSOLUTE MAXIMUM RATINGS(1) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 1. As applicable to the device type. Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) 1 Q2 GND VCC GND GND 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 41 42 43 44 45 46 47 48 1 1 Q1 1 OE 1 Q4 1 Q3 1 Q6 1 Q5 1 Q8 1 Q7 2 Q1 2 Q3 2 Q2 2 Q4 VCC 2 Q5 2 Q6 GND 2 Q7 2 Q8 2 OE 1 D2 GND VCC GND GND 1 D1 1 LE 1 D4 1 D3 1 D6 1 D5 1 D8 1 D7 2 D1 2 D3 2 D2 2 D4 VCC 2 D5 2 D6 GND 2 D7 2 D8 2 LE NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. Inputs Outputs xDx xLE xOE xQx HH L H LH L L XL L Q(2) XX H Z FUNCTION TABLE(1) Pin Names Description xDx Data Inputs xLE Latch Enable Input (Active HIGH) xOE Output Enable Inputs (Active LOW) xQx 3-State Outputs PIN DESCRIPTION |
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