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HCPL-4661 Datasheet(PDF) 6 Page - Agilent(Hewlett-Packard)

No. de pieza HCPL-4661
Descripción Electrónicos  Dual Channel, High CMR, High Speed, TTL Compatible Optocouplers 8 Pin DIP and SOIC-8
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Fabricante Electrónico  HP [Agilent(Hewlett-Packard)]
Página de inicio  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HCPL-4661 Datasheet(HTML) 6 Page - Agilent(Hewlett-Packard)

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6
Parameter
Symbol
Device
Min.
Typ.* Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
75
ns
T
A = 25°C
Time to High
t
PLH
20
48
7, 8, 9
3, 6
Output Level
100
ns
Propagation Delay
75
ns
T
A = 25°C
Time to Low
t
PHL
25
50
7, 8, 9
3, 7
Output Level
100
ns
R
L = 350 Ω
Pulse Width
|t
PHL-tPLH|
3.5
35
ns
C
L = 15 pF
10
13
Distortion
Propagation Delay
t
PSK
40
ns
13,14
Skew
Output Rise Time
t
r
24
ns
11
3
(10-90%)
Output Fall Time
t
f
10
ns
11
3
(90-10%)
Common Mode
HCPL-2630/0630
10,000
V
CM = 10 V
V
O(MIN) = 2 V,
Transient
R
L = 350 Ω,
Immunity at
|CM
H|
HCPL-2631/0631
5,000
10,000
V/
µsV
CM = 50 V
I
F = 0 mA,
12
3, 8,
High Output
T
A = 25°C10
Level
HCPL-4661/0661 10,000 15,000
V
CM = 1000 V
Common Mode
HCPL-2630/0630
10,000
V
CM = 10 V
V
O(MAX) = 0.8 V,
Transient
R
L = 350 Ω,
Immunity at
|CM
L|
HCPL-2631/0631
5,000
10,000
V/
µsV
CM = 50 V
I
F = 7.5 mA
12
3, 9,
Low Output
T
A = 25°C10
Level
HCPL-4661/0661 10,000 15,000
V
CM = 1000 V
Switching Specifications
Over recommended temperature (T
A = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA, unless otherwise
specified.
*All typical values are at V
CC = 5 V, TA = 25°C.
Notes:
1. Bypassing of the power supply line is required with a 0.1
µF ceramic disc capacitor adjacent to each optocoupler. Total lead
length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current
does not exceed 15 mA.
3. Each channel.
4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
8. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic
state (i.e., VOUT > 2.0 V).
9. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic
state (i.e., VOUT < 0.8 V).
10. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p).
11. As illustrated in Figure 15 the VCC and GND traces can be located between the input and the output leads to provide
additional noise immunity at the compromise of insulation capability.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥ 3000 V
RMS for 1 second
(Leakage detection current limit, II-O ≤ 5 µA).
13. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the operating condition range.
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
≥ 6000 V
RMS for 1 second
(Leakage detection current limit, II-O ≤ 5 µA). This option is valid for HCPL-2630/2631/4661 only.
16. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
17. Derate linearly above 80
°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.


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