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AD80C154-36 Datasheet(PDF) 7 Page - TEMIC Semiconductors |
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AD80C154-36 Datasheet(HTML) 7 Page - TEMIC Semiconductors |
7 / 24 page 80C154/83C154 Rev.F (14 Jan. 97) 7 MATRA MHS Table 1. Status of the external pins during idle and power down modes. MODE PROGRAM MEMORY ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Port Data Port Data Port Data Port Data Idle External 1 1 Floating Port Data Address Port Data Power Down Internal 0 0 Port Data Port Data Port Data Port Data Power Down External 0 0 Floating Port Data Port Data Port Data Figure 4. I/O Buffers in the 83C154 (Ports 1, 2, 3). Stop Clock Mode Due to static design, the TEMIC 83C154 clock speed can be reduced until 0 MHz without any data loss in memory or registers. This mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. At 0 MHz, the power consumption is the same as in the Power Down Mode. I/O Ports The I/O drives for P1, P2, P3 of the 83C154 are impedance programmable. The I/O buffers for Ports 1, 2 and 3 are implemented as shown in figure 4. When the port latch contains 0, all pFETS in figure 4 are off while the nFET is turned on. When the port latch makes a 0-to-1 transition, the nFET turns off. The strong pullup pFET, T1, turns on for two oscillator periods, pulling the output high very rapidly. As the output line is drawn high, pFET T3 turns on through the inverter to supply the IOH source current. This inverter and T3 form a latch which holds the 1 and is supported by T2. When Port 2 is used as an address port, for access to external program of data memory, any address bit that contains a 1 will have his strong pullup turned on for the entire duration of the external memory access. When an I/O pin on Ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. The maximum sink current is specified as ITL under the D.C. Specifications. When the input goes below approximately 2 V, T3 turns off to save ICC current. Note, when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the user’s circuit does not force the input line high. The input impedance of Port 1, 2, 2 are programmable through the register IOCON. The ALF bit (IOCON0) set all of the Port 1, 2, 3 floating when a Power Down mode occurs. The P1HZ, P2HZ, P3HZ bits (IOCON1, IOCON2, IOCON3) set respectively the Ports P1, P2, P3 in floating state. The IZC (IOCON4) allows to choose input impedance of all ports (P1, P2, P3). When IZC = 0, T2 and T3 pullup of I/O ports are active ; the internal input impedance is approximately 10 K. When IZC = 1 only T2 pull-up is active. The T3 pull-up is turned off by IZC. The internal impedance is approximately 100 K. Oscillator Characteristics XTAL1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use as an on-chip oscillator, as shown in figure 5. Either a quartz crystal or ceramic resonator may be used. Figure 5. Crystal Oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected as shown in figure 6. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the Data Sheet must be observed. |
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