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DM3730CBPD100 Datasheet(PDF) 2 Page - Texas Instruments |
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DM3730CBPD100 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 280 page DM3730, DM3725 SPRS685D – AUGUST 2010 – REVISED JULY 2011 www.ti.com Bus • Glueless Interface to Common Video Decoders – Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip • Resize Engine Select Pin – Resize Images From 1/4x to 4x – Glueless Interface to NOR Flash, – Separate Horizontal/Vertical Control NAND Flash (With ECC Hamming – System Direct Memory Access (SDMA) Code Calculation), SRAM and Controller (32 Logical Channels With Pseudo-SRAM Configurable Priority) – Flexible Asynchronous Protocol – Comprehensive Power, Reset, and Clock Control for Interface to Custom Logic Management (FPGA, CPLD, ASICs, etc.) • SmartReflexTM Technology – Nonmultiplexed Address/Data Mode • Dynamic Voltage and Frequency Scaling (Limited 2K-Byte Address Space) (DVFS) – 1.8-V I/O and 3.0-V (MMC1 only), – ARM® Cortex™-A8 Core 0.9-V to 1.2-V Adaptive Processor Core • ARMv7 Architecture Voltage – TrustZone® 0.9-V to 1.1-V Adaptive Core Logic Voltage – Thumb®-2 Note: These are default Operating Performance Point (OPP) voltages and could – MMU Enhancements be optimized to lower values using • In-Order, Dual-Issue, Superscalar SmartReflex AVS. Microprocessor Core – Commercial, Industrial, and Extended • NEON Multimedia Architecture Temperature Grades • Over 2x Performance of ARMv6 SIMD – Serial Communication • Supports Both Integer and Floating Point • 5 Multichannel Buffered Serial Ports SIMD (McBSPs) • Jazelle® RCT Execution Environment – 512 Byte Transmit/Receive Buffer Architecture (McBSP1/3/4/5) • Dynamic Branch Prediction with Branch – 5K-Byte Transmit/Receive Buffer Target Address Cache, Global History (McBSP2) Buffer, and 8-Entry Return Stack – SIDETONE Core Support (McBSP2 and • Embedded Trace Macrocell (ETM) 3 Only) For Filter, Gain, and Mix Support for Non-Invasive Debug Operations – ARM Cortex-A8 Memory Architecture: – Direct Interface to I2S and PCM Device • 32K-Byte Instruction Cache (4-Way and T Buses Set-Associative) – 128 Channel Transmit/Receive Mode • 32K-Byte Data Cache (4-Way • Four Master/Slave Multichannel Serial Set-Associative) Port Interface (McSPI) Ports • 256K-Byte L2 Cache • High-Speed/Full-Speed/Low-Speed USB – 32K-Byte ROM OTG Subsystem (12-/8-Pin ULPI Interface) – 64K-Byte Shared SRAM • High-Speed/Full-Speed/Low-Speed – Endianess: Multiport USB Host Subsystem • ARM Instructions - Little Endian – 12-/8-Pin ULPI Interface or 6-/4-/3-Pin • ARM Data – Configurable Serial Interface • DSP Instructions/Data - Little Endian • One HDQ/1-Wire Interface • Removable Media Interfaces: • Four UARTs (One with Infrared Data – Three Multimedia Card (MMC)/ Secure Digital Association [IrDA] and Consumer Infrared (SD) With Secure Data I/O (SDIO) [CIR] Modes) • Test Interfaces • Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers – IEEE-1149.1 (JTAG) Boundary-Scan Compatible – Camera Image Signal Processing (ISP) – Embedded Trace Macro Interface (ETM) • CCD and CMOS Imager Interface – Serial Data Transport Interface (SDTI) • Memory Data Input • 12 32-bit General Purpose Timers • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface • 2 32-bit Watchdog Timers 2 DM3730, DM3725 Digital Media Processors Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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