TSC2046

9

SBAS265C

www.ti.com

ANALOG INPUT

Figure 2 shows a block diagram of the input multiplexer on

the TSC2046, the differential input of the ADC, and the

differential reference of the converter. Table I and Table II

show the relationship between the A2, A1, A0, and SER/DFR

control bits and the configuration of the TSC2046. The

control bits are provided serially via the DIN pin—see the

Digital Interface section of this data sheet for more details.

A2

A1

A0

TEMP

Y–

X+

Y+

Y-POSITION

X-POSITION

X-DRIVERS

Y-DRIVERS

00

0

+IN (TEMP0)

Off

Off

0

0

1

+IN

Measure

Off

On

0

1

0

+IN

Off

Off

0

1

1

+IN

Measure

X–, On

Y+, On

1

0

0

+IN

Measure

X–, On

Y+, On

1

0

1

+IN

Measure

On

Off

1

1

0

+IN

Off

Off

11

1

+IN (TEMP1)

Off

Off

TABLE I. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high).

TABLE II. Input Configuration (DIN), Differential Reference Mode (SER/DFR low).

A2

A1

A0

+REF

–REF

Y–

X+

Y+

Y-POSITION

X-POSITION

DRIVERS ON

0

0

1

Y+

Y–

+IN

Measure

Y+, Y–

0

1

1

Y+

X–

+IN

Measure

Y+, X–

1

0

0

Y+

X–

+IN

Measure

Y+, X–

1

0

1

X+

X–

+IN

Measure

X+, X–

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs (as shown in

Figure 2) is captured on the internal capacitor array. The

input current into the analog inputs depends on the conver-

sion rate of the device. During the sample period, the source

must charge the internal sampling capacitor (typically 25pF).

After the capacitor has been fully charged, there is no further

input current. The rate of charge transfer from the analog

source to the converter is a function of conversion rate.

FIGURE 2. Simplified Diagram of Analog Input.

ADC

Logic

Level

Shifter

+REF

+IN

V

BAT

AUX

Battery

On

GND

2.5V

Reference

Ref On/Off

X+

X–

+V

CC

TEMP1

PENIRQ

50k

Ω

or

90k

Ω

Y+

Y–

V

REF

IOVDD

TEMP0

7.5k

Ω

2.5k

Ω

A2-A0

(Shown 001

SER/DFR

(Shown Low)