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TSB43CA42GGW Datasheet(PDF) 3 Page - Texas Instruments |
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TSB43CA42GGW Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 97 page  TSB43Cx43A/ TI iceLynx-Micro™ IEEE 1394a-2000 TSB43CA42 Consumer Electronics Solution TEXAS INSTRUMENTS SLLS546F – March 2004 – Revised September 2004 PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TEXAS INSTRUMENTS Copyright 2004, Texas Instruments Incorporated MARCH 12, 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 Table of Contents 1 Hardware IC Characteristics.................................................................................................................. 8 1.1 Feature List ................................................................................................................................... 8 1.1.1 1394 Features ......................................................................................................................... 8 1.1.2 DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio (TSB43CA43A and TSB43CA42 Only) ................................................................................................................... 8 1.1.3 High Speed Data Interface (HSDI).......................................................................................... 9 1.1.4 External CPU Interface............................................................................................................ 9 1.1.5 Internal ARM7.......................................................................................................................... 9 1.1.6 Data Buffers............................................................................................................................. 9 1.1.7 Hardware Packet Formatting for the Following Standards ..................................................... 9 1.1.8 Additional Features ................................................................................................................. 9 1.2 Application Diagram.................................................................................................................... 10 1.3 Block Diagram............................................................................................................................. 11 1.3.1 TSB43Cx43A Block Diagram ................................................................................................ 11 1.3.2 TSB43CA42 Block Diagram .................................................................................................. 12 1.4 Pin Out ........................................................................................................................................ 13 1.4.1 TSB43CA43A/TSB43CB43A Plastic Quad Flat Pack (PQFP).............................................. 13 1.4.2 TSB43CA43A/TSB43CB43A Micro-Star Ball Grid Array ( µ*BGA)........................................14 1.4.3 TSB43CA42 Plastic Quad Flat Pack (PQFP)........................................................................ 15 1.4.4 TSB43CA42 Micro-Star Ball Grid Array ( µ*BGA)..................................................................16 1.5 Pin Description............................................................................................................................ 17 1.6 Memory Map ............................................................................................................................... 26 1.7 DTCP Encryption – Hardware Implementation (TSB43CA43A and TSB43CA42 Only) ............ 27 1.8 Program Memory ........................................................................................................................ 27 1.8.1 Overview/Description ............................................................................................................27 1.8.2 External CPU (Parallel Mode) ............................................................................................... 27 1.9 External CPU Interface ............................................................................................................... 27 1.9.1 Overview/Description ............................................................................................................27 1.9.2 Endian Setting (Parallel and Memory Accesses) .................................................................. 29 1.9.3 Ex-CPU Access..................................................................................................................... 30 1.9.4 Ex-CPU Timing...................................................................................................................... 33 1.9.5 LEB Encryption...................................................................................................................... 52 1.10 Integrated CPU ........................................................................................................................... 53 1.10.1 Description/Overview ............................................................................................................53 1.10.2 Interaction With External CPU............................................................................................... 53 1.10.3 External Interrupts ................................................................................................................. 53 1.10.4 Timer ..................................................................................................................................... 54 1.11 High Speed Data Interface ......................................................................................................... 54 1.11.1 Overview/Description ............................................................................................................54 1.11.2 Frame Sync Detection Circuit................................................................................................ 56 1.11.3 HSDI Pass-Through Function ............................................................................................... 56 1.11.4 HSDI Maximum Clock Rates and Throughput ...................................................................... 57 1.11.5 HSDI Mode Settings..............................................................................................................57 1.11.6 HSDI Transmit Modes ........................................................................................................... 59 1.11.7 HSDI Receive Modes ............................................................................................................ 62 1.11.8 Audio Interface on HSDI........................................................................................................66 1.12 UART Interface ........................................................................................................................... 70 1.12.1 UART Registers..................................................................................................................... 70 1.12.2 UART Baud Rate................................................................................................................... 71 1.13 JTAG – Boundary Scan and ARM .............................................................................................. 72 1.14 Integrated 3-Port PHY ................................................................................................................ 72 |
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