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AK4376AECB Datasheet(PDF) 47 Page - Asahi Kasei Microsystems |
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AK4376AECB Datasheet(HTML) 47 Page - Asahi Kasei Microsystems |
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47 / 68 page  [AK4376A] 016014206-E-00 2016/11 - 47 - ■ Charge Pump & LDO Circuits The charge pump circuits are operated by CVDD power supply voltage. CVDD is used to generate negative voltage. The power-up/down sequence of charge pump and LDO circuits are as follows. CP1 should be powered up before LDO1P/N are powered up. CP2 should be powered up after LDO1P/N are powered up. LDO1P and LDO1N blocks must be powered up or down at the same time. Power-Up Sequence: CP1 → LDO1P, LDO1N → CP2 Power-Down Sequence: CP2 → LDO1P, LDO1N → CP1 LDO1P and LDO1N have an overcurrent protection circuit. When overcurrent flows in a normal operation, the LDO1P and LDO1N circuits limit the operation current. If the over current state is cleared, the overcurrent protection will be off and the LDO1P and LDO1N circuits will return to normal operation. LDO2 has an overvoltage protection circuit. This overvoltage protection circuit powers the LDO2 down when the power supply becomes unstable by an instantaneous power failure, etc. during operation. The LDO2 circuit will not return to a normal operation until being reset by the PDN pin ( “L” → “H”) after removing the problems. The charge pump and the LDO circuits can be powered up again while they are in power-down state. Table 28. Input/Output Voltage and Operation Block of the Charge Pump Charge Pump Power Management bit Input Voltage Output Voltage (Typ.) Operation Block CP1 PMCP1 CVDD 1.8 V LDO1N DAC CP2 (Class-G) PMCP2 CVDD 1.8 V / 0.9 V HP Table 29. Input/Output Voltage and Operation Block of the LDO LDO Power Management bit Power Supply Output Voltage (Typ.) Operation Block LDO1P PMLDO1P AVDD / VSS1 +1.5 V VREF+ for DAC, HP LDO1N PMLDO1N VSS1 / CP2 Output 1.5 V VREF for DAC, HP LDO2 - LVDD / VSS1 +1.2 V Digital Core |
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