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AK7755EN Datasheet(PDF) 56 Page - Asahi Kasei Microsystems |
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AK7755EN Datasheet(HTML) 56 Page - Asahi Kasei Microsystems |
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56 / 109 page  [AK7755] 014006643-E-00 2014/10 - 56 - ■ Power-down and Reset 1. Power-down, Reset and Power Management of the AK7755 The AK7755 has four types of power-down and reset functions that are power-down (PDN pin), Clock reset (CLKRESETN bit (CONT01:D0)), CODEC reset (CRESETN bit(CONT0F:D3)) and DSP reset (DSPRESETN bit(CONT0F:D2)). Each block can be powered-down by power management registers. 2. Power-down The AK7755 is powered down by setting the PDN pin = “L”. The PDN pin must be set to “L” when power up the AK7755. The statuses of output pins in power-down mode are shown below. LDOE pin = “L” (External 1.2V supply mode) No Pin Name I/O Power-down Mode Status No Pin Name I/O Power-down Mode Status 1 VCOM O L 17 SO/SDA I/O Hi-Z 6 STO/RDY O H 18 SCLK/SCL I/O Hi-Z 7 LRCK I/O L 26 OUT3 O Hi-Z 8 BICK I/O L 27 OUT2 O Hi-Z 9 CLKO O L 28 OUT1 O Hi-Z 10 XTO O H 31 IN4/INN2/DMCLK2 I/O Hi-Z 11 XTI I H 32 IN3/INP2/DMDAT2 I Hi-Z 14 JX2/SDOUT3/JX2/MAT1 I/O L 33 IN2/INN1/DMCLK1 I/O Hi-Z 15 SDOUT2/JX3/MAT1 I/O L 34 IN1/INP1/DMDAT1 I Hi-Z 16 SDOUT1 O L Note 44. [I/O] indicates Input / Output attribute of each pin. LDOE pin = “H” (LDO mode) No Pin Name I/O Power-down Mode Status No Pin Name I/O Power-down Mode Status 1 VCOM O L 17 SO/SDA I/O Hi-Z 6 STO/RDY O L 18 SCLK/SCL I/O Hi-Z 7 LRCK I/O L 24 AVDRV O L 8 BICK I/O L 26 OUT3 O Hi-Z 9 CLKO O L 27 OUT2 O Hi-Z 10 XTO O H 28 OUT1 O Hi-Z 11 XTI I H 31 IN4/INN2/DMCLK2 I/O Hi-Z 14 JX2/SDOUT3/JX2/MAT1 I/O L 32 IN3/INP2/DMDAT2 I Hi-Z 15 SDOUT2/JX3/MAT1 I/O L 33 IN2/INN1/DMCLK1 I/O Hi-Z 16 SDOUT1 O L 34 IN1/INP1/DMDAT1 I Hi-Z 3. Power-down Release 3- 1. LDOE = “L” (External 1.2V supply mode) DVDD, TVDD and AVDD should be supplied when the PDN pin = “L”. By bringing the PDN pin “H” 600ns (min) after all power supplies are fed (DVDD, TVDD and AVDD), REF voltage circuit (Analog reference voltage) starts operation. Control register write / read should be made 1ms after bringing the PDN pin = “H” (Figure 24). AVDD and TVDD must be powered up first before DVDD. In this case, the power-up sequence between AVDD and TVDD is not critical. 3-2 . LDOE = “H” (LDO mode) TVDD and AVDD should be supplied when the PDN pin = “L”. By bringing the PDN pin “H” 600ns (min) after TVDD and AVDD are fed, the power supply circuits for REF generator and internal digital circuit start operation. Control register write / read should be made 1ms after bringing the PDN pin = “H” (Figure 28). |
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