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TPA3111D1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPA3111D1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 31 page 1 SD 28 PVCC 2 FAULT 27 PVCC 3 GND 26 BSN 4 GND 25 OUTN 5 GAIN0 24 PGND 6 GAIN1 23 OUTN 7 AVCC 22 BSN 8 AGND 21 BSP 9 GVDD 20 OUTP 10 PLIMIT 19 PGND 11 INN 18 OUTP 12 INP 17 BSP 13 NC 16 PVCC 14 AVCC 15 PVCC Not to scale 3 TPA3111D1 www.ti.com SLOS618F – AUGUST 2009 – REVISED JULY 2016 Product Folder Links: TPA3111D1 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. AGND 8 — Analog supply ground. Connect to the thermal pad. AVCC 7 P Analog supply. A 100-kΩ resistor in series with AVCC is needed if the PVCC slew rate is greater than 10 V/ms. AVCC 14 P Connect AVCC supply to this pin. BSP 17 I Bootstrap I/O for positive high-side FET. BSP 21 I Bootstrap I/O for positive high-side FET. BSN 22 I Bootstrap I/O for negative high-side FET. BSN 26 I Bootstrap I/O for negative high-side FET. FAULT 2 O Open-drain output used to display short-circuit or DC Detect Fault status. Voltage compliant to AVCC. Short-circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both short- circuit faults and DC Detect Faults must be reset by cycling PVCC. GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC. GND 3 — Connect to local ground GND 4 — Connect to local ground GVDD 9 O High-side FET gate drive supply. Nominal voltage is 7 V. Can also be used as supply for PLILMIT divider. Add a 1-µF capacitor to ground at this pin. INP 12 I Positive audio input. Biased at 3 V. INN 11 I Negative audio input. Biased at 3 V. NC 13 — Not connected |
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