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L6732C Datasheet(PDF) 7 Page - STMicroelectronics |
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L6732C Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 32 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) L6732C 3 Pin connections and functions 7/32 3 Pin connections and functions Figure 2. Pins connection ( Top view) Table 3. Pin functions Pin n. Name Function 1 PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up this pin to VCCDR with a 10K resistor to obtain a logical signal. 2 SYNCH It is a Master-Slave pin. Two or more devices can be synchronized by simply connecting the SYNCH pins together. The device operating with the highest FSW will be the Master. The Slave devices will operate with 180° phase shift from the Master. The best way to synchronize devices together is to set their FSW at the same value. If it is not used the SYNCH pin can be left floating. 3 SGND All the internal references are referred to this pin. 4 FB This pin is connected to the error amplifier inverting input. Connect it to VOUT through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. 5 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. 6 SS/INH The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10 A through the capacitor. When the voltage at this pin is lower than 0.5V the device is disabled. 1 2 3 4 5 6 11 12 HTSSOP16 13 14 15 16 SGND EAREF FB PGOOD SYNCH COMP VCC LGATE PHASE SS/INH PGND 7 10 VCCDR BOOT HGATE 8 9 OCL OCH Obsolete Product(s) - Obsolete Product(s) |
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