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TP3069WM Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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TP3069WM Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 18 page Connection Diagrams Dual-In-Line Package TLH10578 – 2 Top View Plastic Chip Carrier TLH10578 – 3 Top View Order Number TP3069J See NS Package Number J20A Order Number TP3069N See NS Package Number N20A Order Number TP3069V See NS Package Number V20A Order Number TP3069WM See NS Package Number M20B Pin Description Symbol Function VPOa The non-inverted output of the receive power amplifier GNDA Analog ground All signals are referenced to this pin VPOb The inverted output of the receive power amplifier VPI Inverting input to the receive power amplifier VFRO Analog output of the receive filter VCC Positive power supply pin VCCea5Vg5% FSR Receive frame sync pulse which enables BCLKR to shift PCM data into DR FSR is an 8 kHz pulse train See Figures 2 and 3 for timing details DR Receive data input PCM data is shifted into DR following the FSR leading edge BCLKR The bit clock which shifts data into DR after the FSR leading edge May vary from 64 kHz CLKSEL to 2048 MHz Alternatively may be a logic input which selects either 1536 MHz1544 MHz or 2048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see Table I) MCLKR Receive master clock Must be 1536 MHz 1544 MHz or 2048 MHz May be PDN asynchronous with MCLKX but should be synchronous with MCLKX for best performance When MCLKR is connected continuously low MCLKX is selected for all internal timing When MCLKR is connected continuously high the device is powered down Symbol Function MCLKX Transmit master clock Must be 1536 MHz 1544 MHz or 2048 MHz May be asynchronous with MCLKR Best performance is realized from synchronous operation BCLKX The bit clock which shifts out the PCM data on DX May vary from 64 kHz to 2048 MHz but must be synchronous with MCLKX DX The TRI-STATE PCM data output which is enabled by FSX FSX Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX FSX is an 8 kHz pulse train see Figures 2 and 3 for timing details TSX Open drain output which pulses low during the encoder time slot ANLB Analog Loopback control input Must be set to logic ‘0’ for normal operation When pulled to logic ‘1’ the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the output of the receive switched capacitor low-pass filter and the input to the receive RC active filter is connected to ground This results in the VFRO output being at ground level during analog loopback operation GSX Analog output of the transmit input amplifier Used to externally set gain VFXIb Inverting input of the transmit input amplifier VFXIa Non-inverting input of the transmit input amplifier VBB Negative power supply pin VBBeb5Vg5% 2 |
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