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TPD2S703QDGSRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPD2S703QDGSRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 34 page Thermal Pad 1 VD- 10 D- 2 VD+ 9 D+ 3 GND 8 VREF 4 FLT 7 VPWR 5 EN 6 MODE 1 VD- 10 D- 2 VD+ 9 D+ 3 GND 8 VREF 4 FLT 7 VPWR 5 EN 6 MODE 3 TPD2S703-Q1 www.ti.com SLLSEU8 – MARCH 2017 Product Folder Links: TPD2S703-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Pin Configuration and Functions DGS Package 10-Pin SSOP Top View DSK Package 10-Pin WSON Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 VD– I/O High voltage D– USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD protection 2 VD+ I/O High voltage D+ USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD protection 3 GND Ground Ground pin for internal circuits and IEC ESD clamps 4 FLT O Open-drain fault pin. See Table 1 5 EN I Enable active-low input. Drive EN low to enable the switches. Drive EN high to disable the switches. See Table 1 for mode selection 6 MODE I Selects between device modes. See the Detailed Description section. Acts as LDO reference voltage for mode 1 7 VPWR I 5-V DC supply input for internal circuits. Connect to internal power rail on PCB 8 VREF I/O Pin to set OVP threshold. See the Detailed Description section for instructions on how to set OVP threshold 9 D+ I/O I/O protected low voltage D+ USB data line, connects to transceiver 10 D– I/O Protected low voltage D– USB data line, connects to transceiver |
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