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CDCVF2510PWRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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CDCVF2510PWRG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 16 page www.ti.com SWITCHING CHARACTERISTICS CDCVF2510 SCAS638C – JULY 2001 – REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC, AVCC MIN TYP(1) MAX UNIT Supply current VI = VCC or GND, ICC(2) IO = 0, 3.6 V, 0 V 40 µA (static, output not switching) Outputs: low or high One input at VCC - 0.6 V, ∆I CC Change in supply current 3.3 V to 3.6 V 500 µA Other inputs at VCC or GND Ci Input capacitance VI = VCC or GND 3.3 V 2.5 pF Co Output capacitance VO = VCC or GND 3.3 V 2.8 pF (2) For dynamic ICC vs Frequency, see Figure 8 and Figure 9. over recommended ranges of supply voltage and operating free-air temperature, C L = 25 pF, See (1) and Figure 1 and Figure 2 VCC, AVCC = 3.3 V FROM TO ± 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MAX Phase error time-static (normalized), CLK ↑ = 66 MHz to166 MHz FBIN ↑ -125 125 ps See Figure 3 through Figure 6 tsk(o) Output skew time (2) Any Y Any Y 100 ps Phase error time-jitter (3) Any Y or FBOUT -50 50 CLK = 66 MHz to 100 MHz ps Any Y or FBOUT |70| Jitter(cycle-cycle), See Figure 7 CLK = 100 MHz to Any Y or FBOUT |65| ps 166 MHz Duty cycle f(CLK) > 60 MHz Any Y or FBOUT 45% 55% tr Rise time VO = 0.4 V to 2 V Any Y or FBOUT 0.3 1.1 ns/V tf Fall time VO = 2 V to 0.4 V Any Y or FBOUT 0.3 1.1 ns/V Low-to-high propagation delay tPLH(bypass mode) CLK Any Y or FBOUT 1.8 3.9 ns time, bypass mode High-to-low propagation delay tPHL(bypass mode) CLK Any Y or FBOUT 1.8 3.9 ns time, bypass mode (1) These parameters are not production tested. (2) The tsk(o) specification is only valid for equal loading of all outputs. (3) Calculated per PC DRAM SPEC (tphase error, static - jitter(cycle-to-cycle)). 5 Submit Documentation Feedback |
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