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M74HCT573TTR Datasheet(PDF) 1 Page - STMicroelectronics |
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M74HCT573TTR Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page  1/11 July 2001 s HIGH SPEED: tPD = 21ns (TYP.) at VCC = 4.5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 DESCRIPTION The M74HCT573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is at high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. The M74HCT573 is designed to directly interface HSC2MOS systems with TTL and NMOS components. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HCT573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP M74HCT573B1R SOP M74HCT573M1R M74HCT573RM13TR TSSOP M74HCT573TTR TSSOP DIP SOP |
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