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TDA3681J Datasheet(PDF) 8 Page - NXP Semiconductors |
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TDA3681J Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 28 page 2002 Apr 10 8 Philips Semiconductors Product specification Multiple voltage regulator with switch and ignition buffer TDA3681 FUNCTIONAL DESCRIPTION The TDA3681 is a multiple output voltage regulator with a power switch, intended for use in car radios with or without a microcontroller. Because of the low voltage operation of the car radio, low voltage drop regulators are used. Regulator 2 is in regulation when the backup voltage exceeds 6.5 V for the first time. When regulator 2 is switched on and its output voltage is within its voltage range, the reset output is disabled to release the microcontroller. The reset delay time before release can be extended by an external capacitor (CRES). This start-up feature is included to secure a smooth start-up of the microcontroller at first connection, without uncontrolled switching of regulator 2 during the start-up sequence. The charge on the backup capacitor can be used to supply regulator 2 for a short period when the external supply voltage drops to 0 V (the time depends on the value of the backup capacitor). The output stages of all switchable regulators have an extremely low noise behaviour and good stability, even for small values of the output capacitors. When both regulator 2 and the supply voltages (VP1 and VP2 > 4.5 V) are available, regulators 1 and 3 can be operated by means of one enable input. Regulator 4 and the power switch have a separate enable input. Pin HOLD is normally HIGH but is active LOW. Pin HOLD is connected to an open-collector NPN transistor and must have an external pull-up resistor to operate. The hold output is controlled by a low voltage detection circuit which, when activated, pulls the hold output LOW (enabled). The hold outputs of the regulators are connected to an OR gate inside the IC so that the hold circuit is activated when one or more regulators (1, 3 or 4) are out of regulation for any reason. Each regulator enable input controls its own hold triggering circuit, so that if a regulator is disabled or switched off, the hold circuit for that regulator is disabled. The hold circuit is also controlled by the temperature and load dump protection. Activating the temperature or load dump protection causes a hold (LOW) during the time that the protection is activated. When all regulators are switched off, the hold output is controlled by the battery line VP1, temperature protection and load dump protection. The hold circuit is enabled at low battery voltages. This indicates that it is not possible to get regulator 1 into regulation when switching it on: regulator 1 has the highest output voltage (8.5 V) of all switchable regulators. Therefore, regulator 1 is the most critical regulator with respect to an out of regulation condition caused by a low battery voltage. The hold function includes hysteresis to avoid oscillations when the regulator voltage crosses the hold threshold level. The hold output also becomes active when the power switch is in foldback protection mode, see Fig.8. The block diagram of the hold function is illustrated in Fig.5. All output pins are fully protected. The regulators are protected against load dump (regulators 1, 3 and 4 switch off at supply voltages >18 V) and short-circuit (foldback current protection). The power switch contains a current protection. However, this protection is delayed at short-circuit by the reset delay capacitor (it should be noted that this is the second function of the reset delay capacitor CRES). During this time, the output current is limited to a peak value of at least 3 A (after a delay, the power switch can deliver 1.8 A continuous if VP ≤ 18 V). In a normal situation, the voltage on the reset delay capacitor is approximately 3.5 V (depending on the temperature). The power switch output is approximately VP − 0.4 V. At operating temperature, the power switch can deliver at least 3 A. At high temperature, the switch can deliver approximately 2 A. During an overload condition or a short circuit (VSW <VP − 3.7 V), the voltage on the reset delay capacitor rises 0.6 V above the voltage of regulator 2. This rise time depends on the capacitor connected to pin CRES. During this time, the power switch can deliver more than 3 A. When regulator 2 is out of regulation and generates a reset, the power switch can only deliver 2 A and will immediately go into foldback protection. At supply voltages >17 V, the power switch is clamped at 16 V maximum (to avoid externally connected circuits being damaged by an overvoltage) and the power switch will switch off at load dump. Interfacing with the microcontroller (simple full or semi on/off logic applications) can be realized with an independent ignition Schmitt trigger and ignition output buffer (push-pull output). The timing diagrams are illustrated in Figs 6 and 7. The second supply voltage VP2 is used for the switchable regulators 3 and 4. This input can be connected to a lower supply voltage of ≥6 V to reduce the power dissipation of the TDA3681. A DC-to-DC converter could be used for this purpose. |
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