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RX634 Datasheet(PDF) 80 Page - Renesas Technology Corp

No. de pieza RX634
Descripción Electrónicos  54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RX634 Datasheet(HTML) 80 Page - Renesas Technology Corp

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R01DS0255EJ0100 Rev.1.00
Page 80 of 106
Feb 25, 2015
RX634 Group
5. Electrical Characteristics
5.3.6
Timing of On-Chip Peripheral Modules
Note 1. tPcyc: PCLKB cycle
Note 2. tcac: CAC count clock source cycle
Table 5.24
Timing of On-Chip Peripheral Modules (1)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Item
Symbol
Min.
Max.
Unit*1
Test
Conditions
I/O ports
Input data pulse width
tPRW
1.5
tPcyc
Figure 5.20
MTU/TPU
Input capture input pulse width
Single-edge setting
tTICW
1.5
tPcyc
Figure 5.21
Both-edge setting
2.5
Timer clock pulse width
Single-edge setting
tTCKWH,
tTCKWL
1.5
tPcyc
Figure 5.22
Both-edge setting
2.5
Phase counting
mode
2.5
POE
POE# input pulse width
tPOEW
1.5
tPcyc
Figure 5.23
TMR
Timer clock pulse width
Single-edge setting
tTMCWH,
tTMCWL
1.5
tPcyc
Figure 5.24
Both-edge setting
2.5
SCI
Input clock cycle
Asynchronous
tScyc
4—
tPcyc
Figure 5.25
Clock synchronous
6
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—20
ns
Input clock fall time
tSCKf
—20
ns
Output clock cycle
Asynchronous
tScyc
16
tPcyc
Figure 5.26
Clock synchronous
4
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—20
ns
Output clock fall time
tSCKf
—20
ns
Transmit data delay time
Clock synchronous
tTXD
—40
ns
Receive data setup time
Clock synchronous
tRXS
40
ns
Receive data hold time
Clock synchronous
tRXH
40
ns
A/D converter
Trigger input pulse width
tTRGW
1.5
tPcyc
Figure 5.27
CAC
CACREF input pulse width
tPcyc ≤ tcac*2
tCACREF
4.5 tcac + 3 tPcyc
—ns
tPcyc > tcac*2
5 tcac + 6.5 tPcyc
—ns


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