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S3A7 Datasheet(PDF) 74 Page - Renesas Technology Corp |
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S3A7 Datasheet(HTML) 74 Page - Renesas Technology Corp |
74 / 133 page R01DS0263EU0100 Rev.1.00 Page 74 of 130 Feb 23, 2016 S3A7 2. Electrical Characteristics Figure 2.50 SCI input/output timing in clock synchronous mode Table 2.38 SCI timing (2) (1/2) Conditions: VCC = AVCC0 = VREFH = VCC_USB = 1.6 to 5.5 V, VREFH0 = 2.7 V to AVCC0 Item Symbol Min Max Unit Test conditions Simple SPI SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 2.51 SCK clock cycle input (slave) 6 65536 SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc SCK clock rise and fall time 1.8 V or above tSPCKr, tSPCKf -20 ns 1.6 V or above - 30 Data input setup time Master 2.7 V or above tSU 45 - ns Figure 2.52 to Figure 2.55 2.4 V or above 55 - 1.8 V or above 80 - 1.6 V or above 105- Slave 2.7 V or above 40 - 1.6 V or above 45 - Data input hold time Master tH 33.3 - ns Slave 40 - SS input setup time tLEAD 1- tSPcyc SS input hold time tLAG 1- tSPcyc Data output delay Master 1.8 V or above tOD -40 ns 1.6 V or above - 50 Slave 2.4 V or above - 65 1.8 V or above - 100 1.6 V or above - 125 Data output hold time Master 2.7 V or above tOH –10 - ns 2.4 V or above –20 - 1.8 V or above –30 - 1.6 V or above –40 - Slave –10 - Data rise and fall time Master tDr, tDf -20 ns Slave 1.8 V or above - 20 1.6 V or above - 30 tTXD tRXS tRXH TXDn RXDn SCKn n = 0 to 4, 9 |
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