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S7G2 Datasheet(PDF) 79 Page - Renesas Technology Corp |
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S7G2 Datasheet(HTML) 79 Page - Renesas Technology Corp |
79 / 116 page R01DS0262EU0100 Rev.1.00 Page 79 of 113 Feb 23, 2016 S7G2 2. Electrical Characteristics 2.3.14 SSI Timing Figure 2.53 SSI clock input/output timing Figure 2.54 SSI data transmit and receive timing when SSICR.SCKP = 0 Table 2.29 SSI timing (1) Middle drive output is selected with the port drive capability bit in the PmnPFS register. (2) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the SSI interface, the AC portion of the electrical characteristics is measured for each group. Item Symbol Min Max Unit Test conditions SSI AUDIO_CLK input frequency tAUDIO -50 MHz - Output clock period tO 150 64000 ns Figure 2.53 Input clock period tI 150 64000 ns Clock high pulse width tHC 60 - ns Clock low pulse width tLC 60 - ns Clock rise time tRC -25 ns Data delay tDTR –5 25 ns Figure 2.54, Figure 2.55 Set-up time tSR 25 - ns Hold time tHTR 25 - ns SSIDATA output delay from WS change time TDTRW -25 ns Figure 2.56 SSISCKn tHC tLC tRC tI, tO tSR tHTR tDTR SSISCKn (Input or Output) SSIWSn, SSIDATAn (Input) SSIWSn, SSIDATAn (Output) |
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