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UPD48576209F1 Datasheet(PDF) 37 Page - Renesas Technology Corp

No. de pieza UPD48576209F1
Descripción Electrónicos  576M-BIT Low Latency DRAM
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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UPD48576209F1 Datasheet(HTML) 37 Page - Renesas Technology Corp

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µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1
R10DS0256EJ0101 Rev. 1.01
Page 37 of 53
Jan. 15, 2016
2.16 Read & Write configuration in Multiplexed Address Mode
In multiplexed address mode, the READ and WRITE latencies are increased by one clock cycle. The
µPD48576209/18/36F1 cycle time remains the same, as described in Table 2-7.
Table 2-7. Configuration in Multiplexed Address Mode
Parameter
Configuration
Unit
1
Note1
2
3
4
Note1,2
5
tRC
4
6
8
3
5
tCK
tRL
5
7
9
4
6
tCK
tWL
6
8
10
5
7
tCK
Valid frequency range
266-175
400-175
533-175
200-175
333-175
MHz
Notes 1. BL = 8 is not available.
2. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank.
In this instance the minimum tRC is 4 cycles.
2.17 Refresh Command in Multiplexed Address Mode
Similar to other commands, the refresh command is executed on the next rising clock edge when in the multiplexed
address mode. However, since only bank address is required for AREF, the next command can be applied on the
following clock. The operation of the AREF command and any other command is represented in Figure 2-29.
Figure 2-29. Burst REFRESH Operation
Remark
AREF
: AUTO REFRESH
AC
: Any command
Ax
: First part Ax of address
Ay
: Second part Ay of address
BAp
: Bank p is chosen so that tRC is met.
ADDRESS
CK#
CK
COMMAND
0
1
2
3
4
5
6
7
8
AC
AREF
AREF
AREF
AREF
AREF
AREF
AREF
Don't care
AREF
9
10
Ax
Ay
AC
Ax
Ay
11
BANK
ADDRESS
BAp
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAp
NOP
ADDRESS
CK#
CK
COMMAND
0
1
2
3
4
5
6
7
8
AC
AREF
AREF
AREF
AREF
AREF
AREF
AREF
Don't care
AREF
9
10
Ax
Ay
AC
Ax
Ay
11
BANK
ADDRESS
BAp
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAp
NOP


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