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HT46R003B Datasheet(PDF) 31 Page - Holtek Semiconductor Inc |
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HT46R003B Datasheet(HTML) 31 Page - Holtek Semiconductor Inc |
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31 / 76 page  Rev. 1.00 30 ��ne 1�� �01� Rev. 1.00 31 ��ne 1�� �01� HT46R003B Cost-Effective A/D 8-bit OTP MCU HT46R003B Cost-Effective A/D 8-bit OTP MCU PBPU Register Bit 7 6 5 4 3 2 1 0 Name — — PBPU5 PBPU� PBPU3 PBPU� PBPU1 PBPU0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit7~6 Unimplemented,readas"0" Bit5~0 PBPU5~PBPU0:PortBbit5~bit0pull-highcontrol 0:Disable 1:Enable Port A Wake-up IftheHALTinstructionisexecuted,thedevicewillentertheSleepMode,wherethesystemclockwill stopresultinginpowerbeingconserved,afeaturethatisimportantforbatteryandotherlow-power applications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethe logicconditionononeofthePA0~PA7pinsfromhightolow.AfteraHALTinstructionforcesthe microcontrollerintoenteringtheSleepMode,theprocessorwillremaininalow-powerstateuntil thelogicconditionoftheselectedwake-uppinonPortAchangesfromhightolow.Thisfunction isespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.Notethatpins PA0~PA7canbeselectedindividuallytohavethiswake-upfeatureusinganinternalregisterknown asPAWU,locatedintheDataMemory. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU� PAWU3 PAWU� PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit7~0 PAWU7~PAWU0:PortAbit7~bit0wake-upcontrol 0:Disable 1:Enable I/O Port Control Registers EachporthasitsowncontrolregisterknownasPAC,PBC,whichcontroltheinput/output configuration.Withthiscontrolregister,eachI/Opinwithorwithoutpull-highresistorscanbe reconfigureddynamicallyundersoftwarecontrol.FortheI/Opintofunctionasaninput,the correspondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogic stateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrol registeriswrittenasa“0”,theI/OpinwillbesetasaCMOSoutput.Ifthepiniscurrentlysetasan output,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthatthe programwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusofthe outputpin. PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 PAC6 PAC5 PAC� PAC3 PAC� PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit7~0 PAC7~PAC0:PortAbit7~bit0Input/Outputcontrol 0:Output 1:Input |
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