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HT82A525R Datasheet(PDF) 18 Page - Holtek Semiconductor Inc |
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HT82A525R Datasheet(HTML) 18 Page - Holtek Semiconductor Inc |
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18 / 71 page  Bit No. Label Function 0C Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation. C is also affected by a rotate through carry instruction. 1AC Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction. 2Z Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero 3OV Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. 4 PDF Power down flag 0: After power up or executing the ²CLR WDT² instruction 1: By executing the ²HALT² instruction 5TO Watchdog Time-Out flag 0: After power up or executing the ²CLR WDT² or ²HALT² instruction 1: A watchdog time-out occurred. 6, 7 ¾ Unused bit, read as ²0² Status (0AH) Register Interrupts This device provides external interrupts (INT pin interrupt), USB interrupt, Serial Interface interrupt and internal timer/event counter interrupts. The Interrupt Control Register0 (INTC0;0BH) and interrupt control register1 (INTC1:1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts can are triggered by a falling edge transition of INT), and the related interrupt request flag (EIF; bit4 of the INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active (INT pin), a subroutine call at location 04H occurs. The interrupt flag (EIF) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of the INTC0), caused by a Timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. HT82A525R I/O Type USB 8-Bit OTP MCU with SPI Rev. 1.80 18 March 11, 2016 |
Número de pieza similar - HT82A525R_16 |
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Descripción similar - HT82A525R_16 |
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