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HT82K95E Datasheet(PDF) 22 Page - Holtek Semiconductor Inc |
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HT82K95E Datasheet(HTML) 22 Page - Holtek Semiconductor Inc |
22 / 42 page HT82K95E/HT82K95A Rev. 2.40 22 November 5, 2014 There is a system clock control register implemented to select the clock used in the MCU. This register consists of the USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK). Bit No. Label R/W Function 2~0, 7 ¾¾ Undefined, should be cleared to ²0² 3 USBCKEN R/W USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is en- abled. Otherwise, the USB clock is turned-off. (Default= ²0²) 4 SUSP2 R/W This bit is used to reduce power consumption in the suspend mode. In the normal mode this bit must be cleared to zero (Default=0). In the HALT mode this bit should be set high to reduce power consumption. If in USB mode set this bit LVR OPT must disable 5 PS2_flag R/W This flag is used to show the MCU is under PS2 mode. (Bit=1) This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²) 6 SYSCLK R/W This bit is used to specify the system oscillator frequency used by the MCU. If a 6MHz crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz crystal oscillator or resonator is used, this bit should be cleared to ²0² (default). SCC (1CH) Register Table High Byte Pointer for Current Table Read TBHP (Address 0X1F) Register Bits Labels Read/Write Option Functions TBHP (0X1F) 3~0 PGC3~PGC0 R ¾ Store current table read bit11~bit8 data Options The following table shows all kinds of option in the microcontroller. All of the options must be defined to ensure proper system functioning. No. Option 1 Chip lock bit (by bit) 2 PA0~PA7 pull-high resistor enabled or disabled (by bit) 3 PB0~PB7 pull-high resistor enabled or disabled (by nibble) 4 PC0~PC7 pull-high resistor enabled or disabled (by nibble) 5 PD0~PD7 pull-high resistor enabled or disabled (by nibble) 6 LVR enable or disable 7 WDT enable or disable 8 WDT clock source: fSYS/4 or WDTOSC 9 ²CLRWDT² instruction(s): 1 or 2 10 PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain (by bit) 11 PA0~PA7 wake-up enabled or disabled (by bit) 12 PB0~PB7 wake-up enabled or disabled (by nibble) 13 PC0~PC7 wake-up enabled or disabled (by nibble) 14 PD0~PD7 wake-up enabled or disabled (by nibble) 15 TBHP enable or disable (default disable) |
Número de pieza similar - HT82K95E_14 |
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Descripción similar - HT82K95E_14 |
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