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HT56R22 Datasheet(PDF) 86 Page - Holtek Semiconductor Inc |
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HT56R22 Datasheet(HTML) 86 Page - Holtek Semiconductor Inc |
86 / 127 page HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Rev. 1.30 86 December 26, 2014 If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to al- low interrupt nesting. If the stack is full, the interrupt re- quest will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decre- mented. If immediate service is desired, the stack must be prevented from becoming full. In case of simulta- neous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occur- ring the corresponding flag should be set before the de- vice is in SLEEP or IDLE Mode. External Interrupt For an external interrupt to occur, the global interrupt en- able bit, EMI, and external interrupt enable bits, INT0E and INT1E, must first be set. Additionally the correct in- terrupt edge type must be selected using the INTEDGE register to enable the external interrupt function and to choose the trigger edge type. An actual external inter- rupt will take place when the external interrupt request flag, INT0F or INT1F, is set, a situation that will occur when a transition, whose type is chosen by the edge se- lect bit, appears on the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PA4 and PA6 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the INTC0 register has been set. The pin must also be setup as an input by setting the corresponding PAC.4 and PAC.6 bits in the port control register. When the in- terrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H or 08H, will take place. When the interrupt is ser- viced, the external interrupt request flags, INT0F or INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin will re- main valid even if the pin is used as an external interrupt input. The INTEDGE register is used to select the type of active edge that will trigger the external interrupt. A choice of ei- ther rising and falling edge types can be chosen along with an option to allow both edge types to trigger an ex- ternal interrupt. Note that the INTEDGE register can also be used to disable the external interrupt function. · INTEDGE Register - All Devices Bit 76543210 Name ¾¾¾¾ INT1S1 INT1S0 INT0S1 INT0S0 R/W ¾¾¾¾ R/W R/W R/W R/W POR ¾¾¾¾ 0000 Bit 7~4 unimplemented, read as ²0² Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges |
Número de pieza similar - HT56R22_14 |
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Descripción similar - HT56R22_14 |
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