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8XC552 Datasheet(PDF) 5 Page - NXP Semiconductors |
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8XC552 Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 60 page  Philips Semiconductors 80C51 Family Derivatives 8XC552/562 overview 1996 Aug 06 5 Table 1. 8XC552 Special Function Registers (Continued) SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE PWMP# PWM1# PWM0# PWM prescaler PWM register 1 PWM register 0 FEH FDH FCH 00H 00H 00H RTE# Reset/toggle enable EFH TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40 00H SP Stack pointer 81H 07H S0BUF Serial 0 data buffer 99H xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 S0CON* Serial 0 control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H S1ADR# Serial 1 address DBH SLAVE ADDRESS GC 00H SIDAT# Serial 1 data DAH 00H S1STA# Serial 1 status D9H SC4 SC3 SC2 SC1 SC0 0 0 0 F8H DF DE DD DC DB DA D9 D8 SICON#* Serial 1 control D8H CR2 ENS1 STA ST0 SI AA CR1 CR0 00H STE# Set enable EEH TG47 TG46 SP45 SP44 SP43 SP42 SP41 SP40 C0H TH1 TH0 TL1 TL0 TMH2# TML2# Timer high 1 Timer high 0 Timer low 1 Timer low 0 Timer high 2 Timer low 2 8DH 8CH 8BH 8AH EDH ECH 00H 00H 00H 00H 00H 00H TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TM2CON# Timer 2 control EAH T2IS1 T2IS0 T2ER T2B0 T2P1 T2P0 T2MS1 T2MS0 00H CF CE CD CC CB CA C9 C8 TM2IR#* Timer 2 int flag reg C8H T20V CMI2 CMI1 CMI0 CTI3 CTI2 CTI1 CTI0 00H T3# Timer 3 FFH 00H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. ECT0 BIT SYMBOL FUNCTION IEN1.7 ET2 Enable Timer T2 overflow interrupt(s) IEN1.6 ECM2 Enable T2 Comparator 2 interrupt IEN1.5 ECM1 Enable T2 Comparator 1 interrupt IEN1.4 ECM0 Enable T2 Comparator 0 interrupt IEN1.3 ECT3 Enable T2 Capture register 3 interrupt IEN1.2 ECT2 Enable T2 Capture register 2 interrupt IEN1.1 ECT1 Enable T2 Capture register 1 interrupt IEN1.0 ECT0 Enable T2 Capture register 0 interrupt SU00755 ECT1 ECT2 ECT3 ECM0 ECM1 ECM2 ET2 0 1 2 3 4 5 6 7 (LSB) (MSB) IEN1 (E8H) Figure 2. Timer T2 Interrupt Enable Register (IEN1) |
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