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SN74AUP1G80DCKR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74AUP1G80DCKR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 38 page D CLK Q CLK D Q Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AUP1G80 SCES593F – JULY 2004 – REVISED JULY 2017 SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop 1 1 Features 1 • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) • Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption (ICC = 0.9 µA Maximum) • Low Dynamic-Power Consumption (Cpd = 4.3 pF Typical at 3.3 V) • Low Input Capacitance (Ci = 1.5 pF Typical) • Low Noise – Overshoot and Undershoot <10% of VCC • Ioff Supports Partial-Power-Down Mode Operation • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V) • Wide Operating VCC Range of 0.8 V to 3.6 V • Optimized for 3.3-V Operation • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • tpd = 4.4 ns Maximum at 3.3 V • Suitable for Point-to-Point Applications 2 Applications • Home Automation • Factory Automation • Test and Measurement • Enterprise Switching • Telecom Infrastructure • Personal Electronics • White Goods 3 Description The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see Figure 2). This is a single positive-edge-triggered D-type flip- flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AUP1G80DBV SOT-23 (5) 1.60 mm × 2.90 mm SN74AUP1G80DCK SC70 (5) 1.25 mm × 2.00 mm SN74AUP1G80DRY SON (6) 1.00 mm × 1.45 mm SN74AUP1G80DSF SON (6) 1.00 mm × 1.00 mm SN74AUP1G80YFP DSBGA (6) 0.76 mm × 1.16 mm SN74AUP1G80YZP DSBGA (5) 0.89 mm × 1.39 mm SN74AUP1G80DPW X2SON (5) 0.80 mm × 0.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) |
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