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DAC38RF84IAAV Datasheet(PDF) 3 Page - Texas Instruments

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No. de pieza DAC38RF84IAAV
Descripción Electrónicos  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC38RF84IAAV Datasheet(HTML) 3 Page - Texas Instruments

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
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Copyright © 2016–2017, Texas Instruments Incorporated
Revision History (continued)
Changed x To:
√ in the JESD204B Formats for DAC38RFxx talbe ..................................................................................... 44
Changed JESD204B frame format for LMFSHd=84111 in Table 12 ................................................................................... 45
Changed JESD204B frame format for LMFSHd=44210 in Table 14 ................................................................................... 46
Changed JESD204B frame format for LMFSHd=24410 in Table 16 ................................................................................... 46
Changed JESD204B frame format for LMFSHd=44210 in Table 17 ................................................................................... 46
Changed JESD204B frame format for LMFSHd=88210 in Table 18 ................................................................................... 46
Changed JESD204B frame format for LMFSHd=24410 in Table 19 ................................................................................... 47
Changed JESD204B frame format for LMFSHd=48410 in Table 20 ................................................................................... 47
Changed JESD204B frame format for LMFSHd=24310 in Table 21 ................................................................................... 47
Changed JESD204B frame format for LMFSHd=48310 in Table 22 ................................................................................... 47
Changed Table 33 ................................................................................................................................................................ 60
Changed register field programming values for LMFSHd=24410 and 24310 in Table 36 ................................................... 65
Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in Table 37 .............................................................. 65
Changed the bit positions of N_M1' N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-8 in Table 37 ......................... 65
Deleted ISFIRCD_ENA and ISFIR_AB regsiter fields. Added ISFIR_ENA register field in Inverse Sinc Filter ................... 67
Changed the description of DAC PLL alarm in Alarm Monitoring ........................................................................................ 70
Changed from BIST_ENA to Reserved in Table 56 ............................................................................................................ 91
Changed from BIST_ZERO to Reserved in Table 56 ......................................................................................................... 91
Changed the description of OUTSUM_SEL field in Table 64 ............................................................................................. 97
Changed From: "dummy data generation" To: "distortion enhancement" in Table 111 .................................................... 127
Changed the junction temp and loop filter voltage range for PLL tuning in Figure 167 .................................................... 141


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