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GS82583EQ18GK-400 Datasheet(PDF) 4 Page - GSI Technology |
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GS82583EQ18GK-400 Datasheet(HTML) 4 Page - GSI Technology |
4 / 26 page GS82583EQ18/36GK-500/450/400 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 8/2017 4/26 © 2014, GSI Technology Pin Description Symbol Description Type SA Address — Read Address is registered on CK and Write Address is registered on CK. Input D[35:0] Write Data — Registered on KD and KD during Write operations. D[17:0] - x18 and x36. D[35:18] - x36 only. Input Q[35:0] Read Data — Aligned with CQ and CQ during Read operations. Q[17:0] - x18 and x36. Q[35:18] - x36 only. Output QVLD[1:0] Read Data Valid — Driven high one half cycle before valid Read Data. Output CK, CK Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing control, and for output timing control. Input KD[1:0], KD[1:0] Write Data Input Clocks — Dual single-ended. Used for latching write data inputs. KD0, KD0: latch Write Data (D[17:0] in x36, D[8:0] in x18). KD1, KD1: latch Write Data (D[35:18] in x36, D[17:9] in x18). Input CQ[1:0], CQ[1:0] Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs. Facilitate source-synchronous operation. Output R Read Enable — Registered on CK. R = 0 initiates a Read operation. Input W Write Enable — Registered on CK. W = 0 initiates a Write operation. Input DLL DLL Enable — Weakly pulled High internally. DLL = 0: disables internal DLL. DLL = 1: enables internal DLL. Input RST Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High. Weakly pulled Low internally. Input ZQ Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to program driver impedance. Input ZT ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to program ODT impedance. Input MZT[1:0] ODT Mode Select — Set the ODT state globally for all input groups. Must be tied High or Low. MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0]. MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0]. MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0]. MZT[1:0] = 11: reserved. Input PZT[1:0] ODT Configuration Select — Set the ODT state for various combinations of input groups when MZT[1:0] = 01 or 10. Must be tied High or Low. PZT[1:0] = 00: enables ODT on write data only. PZT[1:0] = 01: enables ODT on write data and input clocks. PZT[1:0] = 10: enables ODT on write data, address, and control. PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control. Input |
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