GS82583EQ18/36GK-500/450/400

288Mb SigmaQuad-IIIe™

Burst of 2 SRAM

Up to 500 MHz

Rev: 1.06 8/2017

1/26

© 2014, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

260-Pin BGA

Commercial Temp

Industrial Temp

Features

• 8Mb x 36 and 16Mb x 18 organizations available

• 500 MHz maximum operating frequency

• 1.0 BT/s peak transaction rate (in billions per second)

• 72 Gb/s peak data bandwidth (in x36 devices)

• Separate I/O DDR Data Buses

• Non-multiplexed DDR Address Bus

• Two operations - Read and Write - per clock cycle

• Burst of 2 Read and Write operations

• 3 cycle Read Latency

• 1.3V nominal core voltage

• 1.2V, 1.3V, or 1.5V HSTL I/O interface

• Configurable ODT (on-die termination)

• ZQ pin for programmable driver impedance

• ZT pin for programmable ODT impedance

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-



compliant BGA package

SigmaQuad-IIIe™ Family Overview

SigmaQuad-IIIe SRAMs are the Separate I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

SRAMs. Although very similar to GSI's second generation of

networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),

these third generation devices offer several new features that

help enable significantly higher performance.

Clocking and Addressing Schemes

The GS82583EQ18/36GK SigmaQuad-IIIe SRAMs are

synchronous devices. They employ three pairs of positive and

negative input clocks; one pair of master clocks, CK and CK,

and two pairs of write data clocks, KD[1:0] and KD[1:0]. All

six input clocks are single-ended; that is, each is received by a

dedicated input buffer.

CK and CK are used to latch address and control inputs, and to

control all output timing. KD[1:0] and KD[1:0] are used solely

to latch data inputs.

Each internal read and write operation in a SigmaQuad-IIIe B2

SRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IIIe B2 SRAM is always one address pin

less than the advertised index depth (e.g. the 16M x 18 has 8M

addressable index).

Parameter Synopsis

Speed Grade

Max Operating Frequency

Read Latency

-500

500 MHz

3 cycles

1.25V to 1.35V

-450

450 MHz

3 cycles

1.25V to 1.35V

-400

400 MHz

3 cycles

1.25V to 1.35V