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74LVC2G240DP Datasheet(PDF) 8 Page - NXP Semiconductors |
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74LVC2G240DP Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 2003 Mar 11 8 Philips Semiconductors Product specification Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state 74LVC2G240 AC CHARACTERISTICS GND = 0 V. Note 1. All typical values are measured at Tamb =25 °C. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nA to nY see Figs 4 and 6 1.65 to 1.95 1.0 4.1 9.5 ns 2.3 to 2.7 0.5 2.6 5.2 ns 2.7 1.0 3.0 5.5 ns 3.0 to 3.6 0.5 2.5 4.6 ns 4.5 to 5.5 0.5 2.0 4.0 ns tPZH/tPZL 3-state output enable time nOE to nY see Figs 5 and 6 1.65 to 1.95 1.5 4.5 10.3 ns 2.3 to 2.7 1.0 2.9 5.6 ns 2.7 1.5 3.4 5.6 ns 3.0 to 3.6 0.5 2.5 4.7 ns 4.5 to 5.5 0.5 2.0 3.8 ns tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 5 and 6 1.65 to 1.95 1.0 3.5 11.6 ns 2.3 to 2.7 0.5 1.9 5.8 ns 2.7 1.0 2.8 4.5 ns 3.0 to 3.6 1.0 2.7 4.4 ns 4.5 to 5.5 0.5 1.9 3.4 ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA to nY see Figs 4 and 6 1.65 to 1.95 1.0 − 11.9 ns 2.3 to 2.7 0.5 − 6.5 ns 2.7 1.0 − 6.9 ns 3.0 to 3.6 0.5 − 5.8 ns 4.5 to 5.5 0.5 − 5.0 ns tPZH/tPZL 3-state output enable time nOE to nY see Figs 5 and 6 1.65 to 1.95 1.5 − 12.9 ns 2.3 to 2.7 1.0 − 7.0 ns 2.7 1.5 − 7.0 ns 3.0 to 3.6 0.5 − 5.9 ns 4.5 to 5.5 0.5 − 4.8 ns tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 5 and 6 1.65 to 1.95 1.0 − 14.1 ns 2.3 to 2.7 0.5 − 7.6 ns 2.7 1.0 − 5.8 ns 3.0 to 3.6 1.0 − 5.7 ns 4.5 to 5.5 0.5 − 4.6 ns |
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