74LVC2G240DP datasheet(2/20 Pages) PHILIPS

No. de pieza	74LVC2G240DP

Descripción Electrónicos	Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state

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Fabricante Electrónico	PHILIPS [NXP Semiconductors]

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2 / 20 page

2003 Mar 11

2

Philips Semiconductors

Product speciﬁcation

Dual buffer/line driver with 5 V tolerant

inputs/outputs; inverting; 3-state

74LVC2G240

FEATURES

• Wide supply voltage range from 1.65 to 5.5 V

• 5 V tolerant input/output for interfacing with 5 V logic

• High noise immunity

• Complies with JEDEC standard:

– JESD8-7 (1.65 to 1.95 V)

– JESD8-5 (2.3 to 2.7 V)

– JESD8B/JESD36 (2.7 to 3.6 V).

•±24 mA output drive (VCC = 3.0 V)

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Inputs accept voltages up to 5 V

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC2G240 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. This

feature allows the use of these devices as translators in a

mixed 3.3 and 5 V environment.

This device is fully specified for partial power-down

applications using Ioff. The Ioff circuitry disables the output,

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC2G240 is a dual inverting buffer/line driver with

3-state outputs. The 3-state outputs are controlled by the

output enable inputs 1OE and 2OE. A HIGH level at

pins nOE causes outputs to assume a high-impedance

OFF-state. Schmitt-trigger action at all inputs makes the

circuit highly tolerant for slower input rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total switching outputs;

∑ (CL × VCC2 × fo) = sum of outputs.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay inputs nA to output nY VCC = 1.8 V; CL = 30 pF; RL =1kΩ

4.1

ns

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

2.6

ns

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

3.0

ns

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

2.5

ns

VCC = 5.0 V; CL = 50 pF; RL = 500 Ω

2.0

ns

CI

input capacitance

2

pF

CPD

power dissipation capacitance per buffer

output enabled; notes 1 and 2

18

pF

output disabled; notes 1 and 2

5

pF

Número de pieza similar - 74LVC2G240DP

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NXP Semiconductors	74LVC2G240DP	101Kb / 16P	Dual inverting buffer/line driver; 3-state Rev. 04-29 February 2008
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74LVC2G240DP Datasheet(PDF) 2 Page - NXP Semiconductors

74LVC2G240DP Datasheet(HTML) 2 Page - NXP Semiconductors

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