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HCPL-900J Datasheet(PDF) 11 Page - Agilent(Hewlett-Packard) |
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HCPL-900J Datasheet(HTML) 11 Page - Agilent(Hewlett-Packard) |
11 / 12 page 11 Propagation Delay, Pulse Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit, which describes how quickly a logic signal propagates through a system as illustrated in Figure 3. The propagation delay from low to high, t PLH, is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low, t PHL, is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. Figure 3. Timing Diagrams to Illustrate Propagation Delay, t PLH and tPHL. Figure 4. Timing Diagrams to Illustrate Propagation Delay Skew. VIN VOUT VOUT VIN tPSK 50% 50% 2.5 V CMOS 2.5 V CMOS Pulse Width Distortion, PWD, is the difference between t PHL and t PLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 – 30% of the minimum pulse width is tolerable. Propagation Delay Skew, t PSK, and Channel-to-Channel Skew, t CSK, are critical parameters to consider in parallel data trans- mission applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through channels of the digital isolators, differences in propaga- tion delays will cause the data to arrive at the outputs of the digital isolators at different times. If this difference in propagation delay is large enough, it will limit the maxi- mum transmission rate at which parallel data can be sent through the digital isolators. t PSK is defined as the difference between the minimum and maximum propagation delays, either t PLH or tPHL, among two or more devices which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operat- ing temperature). t CSK is defined as the difference between the minimum and maximum propaga- tion delays, either t PLH or tPHL, among two or more channels within a single device (applicable to dual and quad channel de- vices) which are operating under the same conditions. As illustrated in Figure 4, if the inputs of two or more devices are switched either ON or OFF at the same time, t PSK is the difference between the minimum propaga- tion delay, either t PLH or tPHL, and the maximum propagation delay, either t PLH or tPHL. As mentioned earlier, t PSK, can determine the maximum parallel data transmission rate. Figure 5 shows the timing diagram of a typical parallel data transmission application with both the clock and data lines being sent through the digital isolators. The figure shows data and clock signals at the inputs and outputs of the digital isolators. In this case, the data is clocked off the rising edge of the clock. Figure 5. Parallel Data Transmission. DATA DATA INPUTS CLOCK OUTPUTS CLOCK tPSK tPSK INPUT OUTPUT 5 V CMOS 2.5 V CMOS 0 V VOH VOL VOUT VIN tPLH tPHL 50% 10% 90% 90% 10% |
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