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74AC245M Datasheet(PDF) 1 Page - STMicroelectronics |
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74AC245M Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 9 page 1/9 April 2001 s HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 244 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC245 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated.. All floating bus terminals during HIGH-Z state must be held HIGH or LOW All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74AC245 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (NON INVERTED) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74AC245B SOP 74AC245M 74AC245MTR TSSOP 74AC245TTR TSSOP DIP SOP |
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