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GS8180QV36BD-200I Datasheet(PDF) 7 Page - GSI Technology

No. de pieza GS8180QV36BD-200I
Descripción Electrónicos  18Mb Burst of 2 SigmaQuad SRAM
Download  28 Pages
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Fabricante Electrónico  GSI [GSI Technology]
Página de inicio  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8180QV36BD-200I Datasheet(HTML) 7 Page - GSI Technology

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Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Beat 1
D0–D8
Beat 1
D9–D17
Beat 2
D0–D8
Beat 2
D9–D17
Written
Unchanged
Unchanged
Written
GS8180QV18/36BD-200/167
Rev: 1.02b 11/2011
7/28
© 2007, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Output Register Control
SigmaQuad SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.


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