AD4020

Data Sheet

Rev. A | Page 6 of 36

TIMING SPECIFICATIONS

Table 2. Digital Interface Timing

Parameter

Symbol

Min

Typ

Max

Unit

CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE

300

320

350

ns

325

ns

TIME BETWEEN CONVERSIONS

555

ns

10

ns

SCK PERIOD

VIO > 2.7 V

9.8

ns

VIO > 1.7 V

12.3

ns

VIO > 2.7 V

20

ns

VIO > 1.7 V

25

ns

SCK LOW TIME

3

ns

SCK HIGH TIME

3

ns

SCK FALLING EDGE TO DATA REMAINS VALID DELAY

1.5

ns

SCK FALLING EDGE TO DATA VALID DELAY

VIO > 2.7 V

7.5

ns

VIO > 1.7 V

10.5

ns

CNV OR SDI LOW TO SDO D17 MSB VALID DELAY (CS MODE)

VIO > 2.7 V

10

ns

VIO > 1.7 V

13

ns

CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY

200

ns

60

ns

CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)

20

ns

SDI VALID SETUP TIME FROM CNV RISING EDGE

2

ns

SDI VALID HOLD TIME FROM CNV RISING EDGE

CS Mode

2

ns

Daisy-Chain Mode

12

ns

SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)

2

ns

SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE)

2

ns

1

The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1.8 MSPS.

2

3

A throughput rate of 1.8 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 71 MHz.

4

A 50% duty cycle is assumed for SCK.

5

1

FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.

SPECIFICATIONS IN TABLE 1.

Figure 2. Voltage Levels for Timing