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AD9266BCPZRL7-40 Datasheet(PDF) 9 Page - Analog Devices |
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AD9266BCPZRL7-40 Datasheet(HTML) 9 Page - Analog Devices |
9 / 33 page AD9266 Data Sheet Rev. B | Page 8 of 32 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns |
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