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AD9244 Datasheet(PDF) 9 Page - Analog Devices |
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AD9244 Datasheet(HTML) 9 Page - Analog Devices |
9 / 37 page AD9244 Rev. C | Page 8 of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 35 DFS 34 AVDD 33 AGND 30 DGND 31 AVDD 32 AGND 36 SENSE 29 DRVDD 28 OTR 27 D13 (MSB) 25 D11 26 D12 2 AGND 3 AVDD 4 AVDD 7 CLK+ 6 CLK– 5 AGND 1 AGND 8 NIC 9 OEB 10 D0 (LSB) 12 D2 11 D1 13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 AD9244 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 5, 32, 33 AGND Analog Ground. 3, 4, 31, 34 AVDD Analog Supply Voltage. 6, 7 CLK–, CLK+ Differential Clock Inputs. 8, 44 NIC No Internal Connection. 9 OEB Digital Output Enable (Active Low). 10 D0 (LSB) Least Significant Bit, Digital Output. 11 to 13, 16 to 21, 24 to 26 D1 to D3, D4 to D9, D10 to D12 Digital Outputs. 14, 22, 30 DGND Digital Ground. 15, 23, 29 DRVDD Digital Supply Voltage. 27 D13 (MSB) Most Significant Bit, Digital Output. 28 OTR Out-of-Range Indicator (Logic 1 Indicates OTR). 35 DFS Data Format Select. Connect to AGND for straight binary, AVDD for twos complement. 36 SENSE Internal Reference Control. 37 VREF Internal Reference. 38 REFGND Reference Ground. 39 to 42 REFB, REFT Internal Reference Decoupling. 43 DCS 50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for external control of both clock edges. 45 CML Common-Mode Reference (0.5 × AVDD). 46, 47 VIN+, VIN– Differential Analog Inputs. 48 VR Internal Bias Decoupling. |
Número de pieza similar - AD9244_17 |
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Descripción similar - AD9244_17 |
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