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AD73322L Datasheet(PDF) 29 Page - Analog Devices

No. de pieza AD73322L
Descripción Electrónicos  Low Cost, Low Power CMOS General-Purpose Dual Analog Front
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AD73322L Datasheet(HTML) 29 Page - Analog Devices

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AD73322L
Rev. A | Page 28 of 48
Each bit will take 1/SCLK and, allowing for any latency between
the receipt of the Rx interrupt and the transmission of the Tx
data, the relationship for successful operation is given by
M/DMCLK > ((N × 16/SCLK) + TINTERRUPT LATENCY)
The interrupt latency will include the time between the ADC
sampling event and the Rx interrupt being generated in the
DSP—this should be 16 SCLK cycles.
Because the AD73322L is configured in cascade mode, each
device must know the number of devices in the cascade because
the data and mixed modes use a method of counting input
frame sync pulses to decide when they should update the DAC
register from the serial input register. Control Register A
contains a 3-bit field (DC0-2) that is programmed by the DSP
during the programming phase. The default condition is that
the field contains 000b, which is equivalent to a single device in
the cascade (see Table 26). However, for cascade operation this
field must contain a binary value that is one less than the
number of devices in the cascade, which is 001b for a single
AD73322L device configuration.
Table 26. Device Count Settings
DC2
DC1
DC0
Cascade Length
0
0
0
1
0
0
1
2
0
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8


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