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ADAV801 Datasheet(PDF) 16 Page - Analog Devices |
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ADAV801 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 61 page  ADAV801 Rev. A | Page 15 of 60 FUNCTIONAL DESCRIPTION ADC SECTION The ADAV801’s ADC section is implemented using a second- order multibit (5 bits) Σ-Δ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 × fS) or one-quarter of the ADC MCLK rate (modulator clock = 64 × fS). The digital decimator consists of a Sinc^5 filter followed by a cascade of three half-band FIR filters. The Sinc decimates by a factor of 16 at 48 kHz and by a factor of 8 at 96 kHz. Each of the half-band filters decimates by a factor of 2. Figure 23 shows the details of the ADC section. By default, the ADC assumes that the MCLK rate is 256 times the sample rate. The ADC can be clocked by a number of different clock sources to control the sample rate. MCLK selection for the ADC is set by Internal Clocking Control Register 1 (Address 0x76). The ADC provides an output word of up to 24 bits in resolution in twos complement format. The output word can be routed to either the output ports, the sample rate converter, or the S/PDIF digital transmitter. REG 0x76 BITS[4:2] REG 0x6F BITS[1:0] ADC MCLK DIVIDER ADC MCLK ADC Figure 23. Clock Path Control on the ADC Programmable Gain Amplifier (PGA) The input of the record channel features a PGA that converts the single-ended signal to a differential signal, which is applied to the analog Σ-Δ modulator of the ADC. The PGA can be programmed to amplify a signal by up to 24 dB in 0.5 dB increments. Figure 24 shows the structure of the PGA circuit. 4kΩ TO 64kΩ 125Ω TO MODULATOR CAPxN CAPxP EXTERNAL CAPACITOR (1nF NPO) EXTERNAL CAPACITOR (1nF NPO) EXTERNAL CAPACITOR (1nF NPO) 8kΩ 8kΩ VREF 4kΩ 125Ω Figure 24. PGA Block Diagram Analog Σ-Δ Modulator The ADC features a second-order, multibit, Σ-Δ modulator. The input features two integrators in cascade followed by a flash converter. This multibit output is directed to a scrambler, followed by a DAC for loop feedback. The flash ADC output is also converted from thermometer coding to binary coding for input as a 5-bit word to the decimator. Figure 25 shows the ADC block diagram. The ADC also features independent digital volume control for the left and right channels. The volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. Each channel also has a peak detector that records the peak level of the input signal. The peak detector register is cleared by reading it. ADC MCLK AMC (REG 0x6E BIT 7) MULTIBIT Σ-Δ MODULATOR DECIMATOR HPF PEAK DETECT VOLUME CONTROL SINC^5 HALF-BAND FILTER MODULATOR CLOCK (6.144MHz MAX) 384kHz 768kHz SINC COMPENSATION 192kHz 384kHz HALF-BAND FILTER 96kHz 192kHz 48kHz 96kHz ÷2 ÷4 Figure 25. ADC Block Diagram |
Número de pieza similar - ADAV801_17 |
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Descripción similar - ADAV801_17 |
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