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TPS2236DAPR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS2236DAPR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page www.ti.com TPS2231 TPS2236 SLVS536B – JULY 2004 – REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) T J = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V, V I(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT II(AUXIN) 200 320 Normal operation II(3.3VIN) 17.5 25 µA of TPS2236 Outputs are unloaded, TJ[–40, II(1.5VIN) 5.5 15 120 °C] (include CPPEx and CPUSBx II(AUXIN) 120 210 logic pullup currents) Normal operation II(3.3VIN) 10 15 µA of TPS2231 II(1.5VIN) 2.5 10 Total input II quiescent current II(AUXIN) 250 440 Shutdown mode of II(3.3VIN) 3.5 20 µA CPUSB = CPPE = 0 V SHDN = 0 V TPS2236 (discharge FETs are on) (include II(1.5VIN) 0.1 20 CPPEx and CPUSBx logic pullup II(AUXIN) 144 270 currents and SHDN pullup current) TJ Shutdown mode of [–40, 120 °C] II(3.3VIN) 3.5 10 µA TPS2231 II(1.5VIN) 0.5 10 II(AUXIN) 40 100 SHDN = 3.3 V, TPS2236 II(3.3VIN) 0.1 100 µA CPUSB = CPPE = 3.3 V (no card II(1.5VIN) 0.1 100 Forward leakage present, discharge FETs are on); Ilkg(FWD) current current measured at input pins II(AUXIN) 20 50 TJ = 120°C, includes RCLKEN TPS2231 II(3.3VIN) 0.1 50 µA pullup current II(1.5VIN) 0.1 50 TJ = 25°C 0.1 10 II(AUXOUT) µA TJ = 120°C 50 VO(AUXOUT) = VO(3.3VOUT)= 3.3 V; Reverse leakage TJ = 25°C 0.1 10 VO(1.5VOUT) = 1.5 V; All voltage inputs Ilkg(RVS) current (TPS2236 II(3.3VOUT) µA are grounded (current measured TJ = 120°C 50 and TPS2231) from output pins going in) TJ = 25°C 0.1 10 II(1.5VOUT) µA TJ = 120°C 50 LOGIC SECTION (SYSRST, SHDNx, STBYx, PERSTx, RCLKENx, OCx, CPUSBx, CPPEx) SYSRST = 3.6 V, sinking 0 1 I(/SYSRST) Input µA SYSRST = 0 V, sourcing 10 30 SHDNx = 3.6 V, sinking 0 1 I(/SHDNx) Input µA SHDNx = 0 V, sourcing 10 30 Logic input STBYx = 3.6 V, sinking 0 1 supply current I(/STBYx) Input µA STBYx = 0 V, sourcing 10 30 I(RCLKENx) Input RCLKENx = 0 V, sourcing 10 30 µA CPUSB or CPPE = 0 V, sinking 0 1 I(/CPUSBx) or Inputs µA I(/CPPEx) CPUSB or CPPE = 3.6 V, sourcing 10 30 High level 2 Logic input V voltage Low level 0.8 RCLEN output low voltage Output IO(RCLKEN) = 60 µA 0.4 V 3.3VOUT falling 2.7 3 PERST assertion threshold of output voltage (PERST asserted when any output voltage falls below the AUXOUT falling 2.7 3 V threshold) 1.5VOUT falling 1.2 1.35 3.3VOUT, AUXOUT, or 1.5VOUT PERST assertion delay from output voltage 500 ns falling 3.3VOUT, AUXOUT, and 1.5VOUT PERST de-assertion delay from output voltage 4 10 20 ms rising within tolerance Max time from SYSRST asserted or PERST assertion delay from SYSRST 500 ns de-asserted 4 |
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