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ADC10D040CIVS Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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ADC10D040CIVS Datasheet(HTML) 9 Page - National Semiconductor (TI) |
9 / 28 page Converter Electrical Characteristics (Continued) The following specifications apply for V A =VD = +3.3 VDC,VDR = +2.5 VDC,VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN (a.c. coupled) = FSR = 1.4 V P-P,CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS =50 Ω,t rc =tfc < 4 ns, NOT offset cor- rected. Boldface limits apply for T A =TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) I D Digital Supply Current PD = LOW, STBY = LOW, d.c. input 9 10 mA (max) PD = LOW, STBY = HIGH 0.1 mA PD = HIGH, STBY = LOW or HIGH 0.1 mA I DR Digital Output Driver Supply Current (Note 10) PD = STBY = LOW, dc input 1.9 2.5 mA (max) PD Power Consumption PD = LOW, STBY = LOW, d.c. input 267 305 mW (max) PD = LOW, STBY = LOW, 1 MHz Input 270 mW PD = LOW, STBY = HIGH 30 mW PD = HIGH, STBY = LOW or HIGH 0.6 mW PSRR1 Power Supply Rejection Ratio Change in Full Scale with 3.0V to 3.6V Supply Change 90 dB PSRR2 Power Supply Rejection Ratio Rejection at output with 10.3 MHz, 250 mV P-P Riding on V A and VD 52 dB AC Electrical Characteristics OS = Low (Multiplexed Mode) The following specifications apply for V A =VD = +3.3 VDC,VDR = +2.5VDC,VREF = 1.4 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c. coupled) = FSR = 1.4 V P-P,CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS =50 Ω,t rc =tfc < 4 ns, NOT offset cor- rected. Boldface limits apply for T A =TMIN to TMAX: all other limits TA = 25˚C (Note 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) f CLK1 Maximum Clock Frequency 45 40 MHz (min) f CLK2 Minimum Clock Frequency 20 MHz Duty Cycle 50 45 55 % (min) % (max) Pipeline Delay (Latency) I Data 2.5 Clock Cycles Q Data 3.0 Clock Cycles t r,tf Output Rise and Fall Times 5 ns t OC Offset Correction Pulse Width 10 ns (min) t OD Output Delay from CLK Edge to Data Valid 13 19 ns (max) t DIQ I/Q Output Delay 13 ns t SKEW I/Q to Data Skew ±200 ps t AD Sampling (Aperture) Delay 2.2 ns t AJ Aperture Jitter <10 ps (rms) t VALID Data Valid Time 7.5 ns Overrange Recovery Time Differential V IN step from 1.5V to 0V 50 ns t WUPD PD Low to 1/2 LSB Accurate Conversion (Wake-Up Time) <1ms t WUSB STBY Low to 1/2 LSB Accurate Conversion (Wake-Up Time) 800 ns www.national.com 9 |
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