Rev: 1.10 8/2000

11/25

© 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS880Z18/36T-11/100/80/66

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables

below for details.

Note:

There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will

operate in the default states as specified in the above table.

Burst Counter Sequences

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after 2 cycles of wake up time.

Mode Pin Functions

Mode Name

Pin Name

State

Function

Burst Order Control

LBO

L

Linear Burst

H or NC

Interleaved Burst

Output Register Control

FT

L

Flow Through

H or NC

Pipeline

Power Down Control

ZZ

L or NC

Active

H

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

A[1:0]

A[1:0]

A[1:0]

A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00