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MT9P001 Datasheet(PDF) 13 Page - ON Semiconductor |
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MT9P001 Datasheet(HTML) 13 Page - ON Semiconductor |
13 / 33 page MT9P001 www.onsemi.com 13 FEATURES Reset The MT9P001 may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset Assert (LOW) RESET_BAR, it is not necessary to clock the device. All registers return to the factory defaults. When the pin is negated (HIGH), the chip resumes normal operation. Soft Reset Set the Reset register field to “1” (R0x0D[0] = 1). All registers except the following will be reset: • Chip_Enable • Synchronize_Changes • Reset • Use_PLL • Power_PLL • PLL_m_Factor • PLL_n_Divider • PLL_p1_Divider When the field is returned to “0,” the chip resumes normal operation. Power Up and Power Down When first powering on the MT9P001, follow this sequence: 1. Ensure RESET_BAR is asserted (LOW). 2. Bring up the supplies. If both the analog and the digital supplies cannot be brought up simultaneously, ensure the digital supply comes up first. 3. Negate RESET_BAR (HIGH) to bring up the sensor. When powering down, be sure to follow this sequence to ensure that I/Os do not load any buses that they are connected to. 1. Assert RESET_BAR. 2. Remove the supplies. Clocks The MT9P001 requires one clock (EXTCLK), which is nominally 96 MHz. By default, this results in pixels being output on the DOUT pins at a maximum data rate of 96 Mp/s. With VDD_IO = 1.8 V, maximum master clock and maximum data rate become 48 MHz and 48 Mp/s, respectively. The EXTCLK clock can be divided down internally by setting Divide_Pixel_Clock to a non-zero value. This slows down the operation of the chip as though EXTCLK had been divided externally. fEXTCLK if Divide_Pixel_Clock = 0 fPIXCLK= { fEXTCLK / (2 × Divide_Pixel_Clock) otherwise The DOUT, LV, FV, and STROBE outputs are launched on the rising edge of PIXCLK, and should be captured on the falling edge of PIXCLK. The specific relationship of PIXCLK to these other outputs can be adjusted in two ways. If Invert_Pixel_Clock is set, the sense of PIXCLK is inverted from that shown in Figure 8. In addition, if the pixel clock has been divided by Divide_Pixel_Clock, it can be shifted relative to the other outputs by setting Shift_Pixel_Clock. PLL-Generated Master Clock The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and another divider stage to generate the output clock. The clocking structure is shown in Figure 13. PLL control registers can be programmed to generate desired master clock frequency. NOTE:The PLL control registers must be programmed while the sensor is in the software Standby state. The effect of programming the PLL divisors while the sensor is in the streaming state is undefined. Figure 13. PLL-Generated Master Clock EXTCLK PLL Output Clock PLL_n_divider +1 Pre PLL PLL Input Clock (VCO) Div 1 PLL_p1_divider +1 PLL_m_factor SYSCLK (PIXCLK) N M P1 |
Número de pieza similar - MT9P001_17 |
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Descripción similar - MT9P001_17 |
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